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ClockDivider
.
Behavioral
Behavioral Architecture Reference
Inheritance diagram for Behavioral:
[
legend
]
List of all members.
Processes
PROCESS_9
(
CLK_Divider_CLR
,
CLK_Divider_CLK
)
Signals
tmp_clk
std_logic
count
integer
range
0
to
2500000
The documentation for this class was generated from the following file:
testFPGA/ClockDivider.vhd
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Generated on Tue Apr 10 20:26:43 2012 for Microprocessor 8-bit by
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