CU Entity Reference

Inheritance diagram for CU:
fsm struct MP

List of all members.



Architectures

fsm Architecture

Libraries

ieee 

Packages

std_logic_1164 
std_logic_arith 
std_logic_unsigned 

Ports

ADD  in std_logic
 Add instruction.
CLK  in std_logic
 Positive edge trigger clock.
CLR  in std_logic
 Active high asynchronous clear.
LDA  in std_logic
 Load Accumulator instruction.
O  in std_logic
 Out instruction.
SUB  in std_logic
 Sub instruction.
CON  out std_logic_vector ( 11 downto 0 )
 12-bit control word forming control bus ~ ~ ~ ~ ~ ~ ~ ~ CpEpLmCE LiEiLaEa SuEuLbLo

The documentation for this class was generated from the following file:
Generated on Wed Apr 11 09:49:20 2012 for Microprocessor 8-bit by  doxygen 1.6.3