PC Entity Reference

Inheritance diagram for PC:
behave struct MP

List of all members.



Architectures

behave Architecture

Libraries

ieee 

Packages

std_logic_1164 
std_logic_unsigned 

Ports

ep  in std_logic
 Active high otuput enable from PC, or tri-state.
clr  in std_logic
 Active high asynchronous clear.
clk  in std_logic
 Falling edge clock.
cp  in std_logic
 Active high enable PC to count.
q  out std_logic_vector ( 3 downto 0 )
 4-bit PC output

The documentation for this class was generated from the following file:
Generated on Wed Apr 11 09:49:22 2012 for Microprocessor 8-bit by  doxygen 1.6.3