Components | |
AC | <Entity AC> |
ALU | <Entity ALU> |
B_Reg | <Entity B_Reg> |
CU | <Entity CU> |
IR | <Entity IR> |
IRDec | <Entity IRDec> |
MAR | <Entity MAR> |
PC | <Entity PC> |
ROM_16_8 | <Entity ROM_16_8> |
O | <Entity O> |
Signals | |
Ce | std_logic |
Chip select for ROM. | |
D | std_logic_vector ( 3 DOWNTO 0 ) |
MAR 4-bit address input. | |
Eu | std_logic |
Enable ALU. | |
Lm | std_logic |
Content of PC are latched into MAR on the next +ve edge (LOW). | |
Q2 | std_logic_vector ( 3 DOWNTO 0 ) |
MAR 4-bit address output. | |
Su | std_logic |
Add or Sub. | |
W | std_logic_vector ( 7 DOWNTO 0 ) |
W-bus the major internal data bus. | |
add | std_logic |
IR decoder add control signal. | |
con | std_logic_vector ( 11 DOWNTO 0 ) |
Control word bus. | |
Cp | std_logic |
Chip select PC. | |
d1 | std_logic_vector ( 7 DOWNTO 0 ) |
8-bit output data to Adder-Subtractor block | |
Ea | std_logic |
Enable AC. | |
Ei | std_logic |
Enable IR. | |
Ep | std_logic |
Enable PC. | |
La | std_logic |
Load Accumulator AC. | |
Lb | std_logic |
Load B Register B. | |
lda | std_logic |
Load Accumulator instruction. | |
Li | std_logic |
Load Instruction Register IR. | |
Lo | std_logic |
Load Output Register O. | |
output | std_logic |
Output the result. | |
q | std_logic_vector ( 3 DOWNTO 0 ) |
4-bit PC output | |
q1 | std_logic_vector ( 7 DOWNTO 0 ) |
ALU B input 8-bit from B-register. | |
q_alu | std_logic_vector ( 7 DOWNTO 0 ) |
ALU A input 8-bit from AC. | |
q_c | std_logic_vector ( 3 DOWNTO 0 ) |
IR 4-bit output control word to Control-Sequencer block. | |
q_w | std_logic_vector ( 3 DOWNTO 0 ) |
IR 4-bit output data word to W-bus. | |
sub | std_logic |
IR decoder sub control signal. | |
Component Instantiations | |
Accumulator | AC <Entity AC> |
AddSub | ALU <Entity ALU> |
BReg | B_Reg <Entity B_Reg> |
CPU | CU <Entity CU> |
IRReg | IR <Entity IR> |
IRDecoder | IRDec <Entity IRDec> |
MemoryAddressReg | MAR <Entity MAR> |
ProgramCounter | PC <Entity PC> |
ROM | ROM_16_8 <Entity ROM_16_8> |
OReg | O <Entity O> |