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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [compile.modelsim] - Rev 45
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#!/bin/cshif(! -e work) thenvlib workelse\rm -rf workvlib workendifif($1 == "core") then # run SDRAM Core level test casevlog -work work +define+$2 -f filelist_core.felse # Run SDRAM Top Level test casesvlog -work work +define+$2 -f filelist_top.fendif
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