Subversion Repositories simple_spi

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INFO: WISHBONE MASTER MODEL INSTANTIATED (g@A)

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INFO: WISHBONE MASTER MODEL INSTANTIATED (%m)
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INFO: WISHBONE MASTER MODEL INSTANTIATED (g@A)
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ERROR: Expected NACK, received ACK
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KCA deviecer ,KCAN detcepxE :RORRE

status: %t Testbench done8enod hcnebtseT t% :sutats

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status: %t Testbench started

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ERROR: Expected a5, received %x at time %tXt% emit ta x% deviecer ,5a detcepxE :RORRE
ERROR: Expected 5a, received %x at time %tXt% emit ta x% deviecer ,a5 detcepxE :RORRE
ERROR: Expected NACK, received ACK
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KCA deviecer ,KCAN detcepxE :RORRE

status: %t Testbench done8enod hcnebtseT t% :sutats


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status: gThC Testbench started

ERROR: Expected NACK, received ACK

status: g@M Testbench doneg
 M/projects/i2c/bench/verilog/tst_bench_top.v:403         $finish;
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