Lattice Mapping Report File for Design Module 'display_driver_wrapper'
Design Information
Command line: map -a ECP5UM5G -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial
DisplayDriverwDecoder_impl1.ngd -o DisplayDriverwDecoder_impl1_map.ncd -pr
DisplayDriverwDecoder_impl1.prf -mp DisplayDriverwDecoder_impl1.mrp -lpf C:
/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_B
uild/impl1/DisplayDriverwDecoder_impl1_synplify.lpf -lpf C:/Projects/single
-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriv
erwDecoder.lpf -gui -msgset C:/Projects/single-14-segment-display-driver-w-
decoder/Project/Lattice_FPGA_Build/promote.xml
Target Vendor: LATTICE
Target Device: LFE5UM5G-45FCABGA381
Target Performance: 8
Mapper: sa5p00g, version: Diamond (64-bit) 3.8.0.115.3
Mapped on: 01/18/17 01:08:21
Design Summary
Number of registers: 13 out of 44457 (0%)
PFU registers: 12 out of 43848 (0%)
PIO registers: 1 out of 609 (0%)
Number of SLICEs: 65 out of 21924 (0%)
SLICEs as Logic/ROM: 65 out of 21924 (0%)
SLICEs as RAM: 0 out of 16443 (0%)
SLICEs as Carry: 5 out of 21924 (0%)
Number of LUT4s: 127 out of 43848 (0%)
Number used as logic LUTs: 117
Number used as distributed RAM: 0
Number used as ripple logic: 10
Number used as shift registers: 0
Number of PIO sites used: 19 out of 203 (9%)
Number of PIO sites used for single ended IOs: 17
Number of PIO sites used for differential IOs: 2 (represented by 1 PIO
comps in NCD)
Number of block RAMs: 0 out of 108 (0%)
Number of GSRs: 1 out of 1 (100%)
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
DTR used : No
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSOB): 0 out of 4 (0%)
Number of DCC: 0 out of 60 (0%)
Number of DCS: 0 out of 2 (0%)
Number of PLLs: 0 out of 4 (0%)
Number of DDRDLLs: 0 out of 4 (0%)
Number of CLKDIV: 0 out of 4 (0%)
Number of ECLKSYNC: 0 out of 10 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Number of DCUs: 0 out of 2 (0%)
Number of DCU Channels: 0 out of 4 (0%)
Number of EXTREFs: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number Of Mapped DSP Components:
--------------------------------
MULT18X18D 0
MULT9X9D 0
ALU54B 0
ALU24B 0
PRADD18A 0
PRADD9A 0
--------------------------------
Number of Used DSP MULT Sites: 0 out of 144 (0 %)
Number of Used DSP ALU Sites: 0 out of 72 (0 %)
Number of Used DSP PRADD Sites: 0 out of 144 (0 %)
Number of clocks: 1
Net clk_c: 9 loads, 9 rising, 0 falling (Driver: PIO clk )
Number of Clock Enables: 1
Net bttn_state_fifo_0io_RNIB9K02[0]: 5 loads, 5 LSLICEs
Number of local set/reset loads for net n_rst_c merged into GSR: 8
Number of LSRs: 1
Net n_rst_c: 3 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net symbol_scan_cntr[1]: 107 loads
Net symbol_scan_cntr[2]: 107 loads
Net symbol_scan_cntr[3]: 107 loads
Net symbol_scan_cntr[5]: 86 loads
Net symbol_scan_cntr[6]: 57 loads
Net symbol_scan_cntr[4]: 29 loads
Net symbol_scan_cntr[0]: 15 loads
Net n_rst_c: 6 loads
Net bttn_state_fifo_0io_RNIB9K02[0]: 5 loads
Net bttn_state_fifo[0]: 3 loads
Number of warnings: 4
Number of errors: 0
Design Errors/Warnings
WARNING - map: C:/Projects/single-14-segment-display-driver-w-decoder/Project/La
ttice_FPGA_Build/DisplayDriverwDecoder.lpf(29): Semantic error in "USERCODE
ASCII "G.L." ; ": Invalid Ascii char <.>.Invalid Ascii char <.>.. This
preference has been disabled.
WARNING - map: Preference parsing results: 1 semantic error detected.
WARNING - map: Using local reset signal 'n_rst_c' to infer global GSR net.
WARNING - map: There are semantic errors in the preference file C:/Projects/sing
le-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDr
iverwDecoder.lpf.
IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| disp_data_q[0] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| clk | INPUT | LVDS | |
+---------------------+-----------+-----------+------------+
| disp_data_q[14] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[13] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[12] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[11] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[10] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[9] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[8] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[7] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[6] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[5] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[4] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[3] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[2] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| disp_data_q[1] | OUTPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
| button | INPUT | LVCMOS25 | IN |
+---------------------+-----------+-----------+------------+
| n_rst | INPUT | LVCMOS25 | |
+---------------------+-----------+-----------+------------+
Removed logic
Block GND undriven or does not drive anything - clipped.
Signal n_rst_c_i was merged into signal n_rst_c
Signal VCC undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_cry_0_S0[0] undriven or does not drive anything -
clipped.
Signal N_1 undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_s_0_S1[7] undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_s_0_COUT[7] undriven or does not drive anything -
clipped.
Block n_rst_pad_RNIQVTF was optimized away.
Block VCC was optimized away.
Memory Usage
GSR Usage
---------
GSR Component:
The local reset signal 'n_rst_c' of the design has been inferred as Global
Set Reset (GSR). The reset signal used for GSR control is 'n_rst_c'.
GSR Property:
The design components with GSR property set to ENABLED will respond to global
set reset while the components with GSR property set to DISABLED will
not.
Components on inferred reset domain with GSR Property disabled
--------------------------------------------------------------
These components have the GSR property set to DISABLED and are on the
inferred reset domain. The components will respond to the reset signal
'n_rst_c' via the local reset on the component and not the GSR component.
Type and number of components of the type:
Register = 4
Type and instance name of component:
Register : bttn_state_fifo[3]
Register : bttn_state_fifo_0io[0]
Register : bttn_state_fifo[1]
Register : bttn_state_fifo[2]
Run Time and Memory Usage
-------------------------
Total CPU Time: 1 secs
Total REAL Time: 3 secs
Peak Memory Usage: 152 MB
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