PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Wed Jan 18 01:08:29 2017
C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
DisplayDriverwDecoder_impl1.prf -gui -msgset
C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml
Preference file: DisplayDriverwDecoder_impl1.prf.
Cost Table Summary
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 -1.238 7103 0.178 0 25 Complete
* : Design saved.
Total (real) run time for 1-seed: 25 secs
par done!
Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"
Wed Jan 18 01:08:29 2017
Best Par Run
PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
Preference file: DisplayDriverwDecoder_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.
Design name: display_driver_wrapper
NCD version: 3.3
Vendor: LATTICE
Device: LFE5UM5G-45F
Package: CABGA381
Performance: 8
Loading device for application par from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status: Final Version 1.36.
Performance Hardware Data Status: Final Version 50.1.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 19/245 7% used
19/203 9% bonded
IOLOGIC 1/245 <1% used
SLICE 65/21924 <1% used
GSR 1/1 100% used
Number of Signals: 131
Number of Connections: 657
Pin Constraint Summary:
18 out of 18 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
clk_c (driver: clk, clk/ce/sr load #: 9/0/0)
Signal n_rst_c is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 4 secs
Starting Placer Phase 1.
.......................
Placer score = 63578.
Finished Placer Phase 1. REAL time: 15 secs
Starting Placer Phase 2.
.
Placer score = 63553
Finished Placer Phase 2. REAL time: 15 secs
Clock Report
Global Clock Resources:
CLK_PIN : 0 out of 12 (0%)
GR_PCLK : 1 out of 12 (8%)
PLL : 0 out of 4 (0%)
DCS : 0 out of 2 (0%)
DCC : 0 out of 60 (0%)
CLKDIV : 0 out of 4 (0%)
Quadrant TL Clocks:
PRIMARY : 0 out of 16 (0%)
Quadrant TR Clocks:
PRIMARY : 0 out of 16 (0%)
Quadrant BL Clocks:
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 1
PRIMARY : 1 out of 16 (6%)
Quadrant BR Clocks:
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 8
PRIMARY : 1 out of 16 (6%)
Edge Clocks:
No edge clock selected.
+
I/O Usage Summary (final):
19 out of 245 (7.8%) PIO sites used.
19 out of 203 (9.4%) bonded PIO sites used.
Number of PIO comps: 18; differential: 1.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+------------+------------+
| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+----------------+------------+------------+------------+
| 0 | 0 / 27 ( 0%) | - | - | - |
| 1 | 0 / 33 ( 0%) | - | - | - |
| 2 | 1 / 32 ( 3%) | 2.5V | - | - |
| 3 | 14 / 33 ( 42%) | 2.5V | - | - |
| 6 | 2 / 33 ( 6%) | 1.2V | - | - |
| 7 | 0 / 32 ( 0%) | - | - | - |
| 8 | 2 / 13 ( 15%) | 2.5V | - | - |
+----------+----------------+------------+------------+------------+
Total placer CPU time: 14 secs
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
0 connections routed; 657 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 22 secs
Start NBR router at 01:08:51 01/18/17
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 01:08:52 01/18/17
Start NBR section for initial routing at 01:08:52 01/18/17
Level 1, iteration 1
0(0.00%) conflict; 544(82.80%) untouched conns; 8380 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.227ns/-8.380ns; real time: 23 secs
Level 2, iteration 1
0(0.00%) conflict; 542(82.50%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 23 secs
Level 3, iteration 1
0(0.00%) conflict; 523(79.60%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 23 secs
Level 4, iteration 1
5(0.00%) conflicts; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 23 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 01:08:53 01/18/17
Level 1, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 2, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 3, iteration 1
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Start NBR section for performance tuning (iteration 1) at 01:08:53 01/18/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Start NBR section for re-routing at 01:08:53 01/18/17
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
Estimated worst slack/total negative slack<setup>: -1.238ns/-8.800ns; real time: 24 secs
Start NBR section for post-routing at 01:08:53 01/18/17
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 9 (1.37%)
Estimated worst slack<setup> : -1.238ns
Timing score<setup> : 7103
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 24 secs
Total REAL time: 25 secs
Completely routed.
End of route. 657 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 7103
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = -1.238
PAR_SUMMARY::Timing score<setup/<ns>> = 7.103
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.178
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 25 secs
Total REAL time to completion: 26 secs
par done!
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.