Synthesis Report
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
#install: C:\lscc\diamond\3.8_x64\synpbase
#OS: Windows 8 6.2
#Hostname: DESKTOP-1AUKF7V
# Tue Jan 17 01:19:09 2017
#Implementation: impl1
Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
VHDL syntax check successful!
Compiler output is up to date. No re-compile necessary
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
Post processing for work.rom128x1a.syn_black_box
Post processing for work.distromasciidecoder.structure
Post processing for work.asciidecoder.arch
Post processing for work.displaydriverwdecoder_top.arch
Post processing for work.displaydriverwrapper.arch
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Tue Jan 17 01:19:09 2017
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Tue Jan 17 01:19:09 2017
###########################################################]
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Tue Jan 17 01:19:09 2017
###########################################################]
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
@N|Running in 64-bit mode
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Tue Jan 17 01:19:11 2017
###########################################################]
Pre-mapping Report
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
@A: MF827 |No constraint file specified.
@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt
Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Clock Summary
*****************
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
========================================================================================================
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:11 2017
###########################################################]
Map & Optimize Report
Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Available hyper_sources - for debug and ip models
None Found
@N: MT206 |Auto Constrain mode is enabled
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.70ns 1 / 8
2 0h:00m:00s -0.70ns 1 / 8
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
3 0h:00m:00s -0.64ns 1 / 9
4 0h:00m:00s -0.64ns 1 / 9
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
@S |Clock Optimization Summary
#### START OF CLOCK OPTIMIZATION REPORT #####[
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001 button port 9 symbol_scan_cntr[0]
===========================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######]
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 17 01:19:13 2017
#
Top view: DisplayDriverWrapper
Requested Frequency: 443.5 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
Performance Summary
*******************
Worst slack in design: -0.398
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
=====================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
=================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: DisplayDriverWrapper|button
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
================================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
==============================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
Number of logic level(s): 4
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
Path information for path number 2:
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
- Propagation time: 2.442
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -0.398
Number of logic level(s): 4
Starting point: symbol_scan_cntr[2] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[2] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
===========================================================================================
Path information for path number 3:
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
Number of logic level(s): 3
Starting point: symbol_scan_cntr[3] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[3] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
Path information for path number 4:
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
Number of logic level(s): 3
Starting point: symbol_scan_cntr[4] / Q
Ending point: symbol_scan_cntr[7] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[4] Net - - - - 15
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[6] Net - - - - 1
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[7] Net - - - - 1
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
===========================================================================================
Path information for path number 5:
Requested Period: 2.255
- Setup time: 0.211
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 2.044
- Propagation time: 2.382
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -0.339
Number of logic level(s): 3
Starting point: symbol_scan_cntr[1] / Q
Ending point: symbol_scan_cntr[5] / D
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
symbol_scan_cntr[1] Net - - - - 15
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
symbol_scan_cntr_cry[2] Net - - - - 1
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
symbol_scan_cntr_cry[4] Net - - - - 1
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
symbol_scan_cntr_s[5] Net - - - - 1
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
===========================================================================================
##### END OF TIMING REPORT #####]
Constraints that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
---------------------------------------
Resource Usage Report
Part: lfe5um5g_45f-8
Register bits: 9 of 43848 (0%)
PIC Latch: 0
I/O cells: 18
Details:
CCU2C: 5
FD1S3DX: 9
GSR: 1
IB: 2
INV: 1
OB: 16
PUR: 1
ROM128X1A: 14
VHI: 1
VLO: 1
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
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