Map TRACE Report
Loading design for application trce from file displaydriverwdecoder_impl1_map.ncd.
Design name: display_driver_wrapper
NCD version: 3.3
Vendor: LATTICE
Device: LFE5UM5G-45F
Package: CABGA381
Performance: 8
Loading device for application trce from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status: Final Version 1.36.
Performance Hardware Data Status: Final Version 50.1.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.8.0.115.3
Wed Jan 18 01:08:27 2017
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o DisplayDriverwDecoder_impl1.tw1 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.prf
Design file: displaydriverwdecoder_impl1_map.ncd
Preference file: displaydriverwdecoder_impl1.prf
Device,speed: LFE5UM5G-45F,8
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_c" 369.959000 MHz (0 errors) 68 items scored, 0 timing errors detected.
Report: 370.096MHz is the maximum frequency for this preference.
Report Type: based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_c" 369.959000 MHz ;
68 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.001ns
The internal maximum frequency of the following component is 370.096 MHz
Logical Details: Cell type Pin name Component name
Destination: SIOLOGIC CLK button_MGIOL
Delay: 2.702ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 1.063ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q bttn_state (from clk_c +)
Destination: FF Data in symbol_scan_cntr[7] (to clk_c +)
Delay: 1.749ns (43.2% logic, 56.8% route), 3 logic levels.
Constraint Details:
1.749ns physical path delay SLICE_7 to SLICE_0 meets
2.703ns delay constraint less
-0.109ns CE_SET requirement (totaling 2.812ns) by 1.063ns
Physical Path Details:
Data path SLICE_7 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.395 SLICE_7.CLK to SLICE_7.Q0 SLICE_7 (from clk_c)
ROUTE 1 e 0.419 SLICE_7.Q0 to SLICE_64.B1 bttn_state_i
CTOF_DEL --- 0.180 SLICE_64.B1 to SLICE_64.F1 SLICE_64
ROUTE 1 e 0.156 SLICE_64.F1 to SLICE_64.A0 G_15_1
CTOF_DEL --- 0.180 SLICE_64.A0 to SLICE_64.F0 SLICE_64
ROUTE 5 e 0.419 SLICE_64.F0 to SLICE_0.CE bttn_state_fifo_0io_RNIB9K02[0] (to clk_c)
--------
1.749 (43.2% logic, 56.8% route), 3 logic levels.
Report: 370.096MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_c" 369.959000 MHz ; | 369.959 MHz| 370.096 MHz| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: clk_c Source: clk.PAD Loads: 9
Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 68 paths, 1 nets, and 50 connections (7.61% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.8.0.115.3
Wed Jan 18 01:08:28 2017
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o DisplayDriverwDecoder_impl1.tw1 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.prf
Design file: displaydriverwdecoder_impl1_map.ncd
Preference file: displaydriverwdecoder_impl1.prf
Device,speed: LFE5UM5G-45F,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_c" 369.959000 MHz (0 errors) 68 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_c" 369.959000 MHz ;
68 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.104ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q bttn_state_fifo[1] (from clk_c +)
Destination: FF Data in bttn_state_fifo[2] (to clk_c +)
Delay: 0.222ns (73.9% logic, 26.1% route), 1 logic levels.
Constraint Details:
0.222ns physical path delay SLICE_5 to SLICE_5 meets
0.118ns M_HLD and
0.000ns delay constraint requirement (totaling 0.118ns) by 0.104ns
Physical Path Details:
Data path SLICE_5 to SLICE_5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.164 SLICE_5.CLK to SLICE_5.Q0 SLICE_5 (from clk_c)
ROUTE 3 e 0.058 SLICE_5.Q0 to SLICE_5.M1 bttn_state_fifo[1] (to clk_c)
--------
0.222 (73.9% logic, 26.1% route), 1 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_c" 369.959000 MHz ; | 0.000 ns| 0.104 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: clk_c Source: clk.PAD Loads: 9
Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 68 paths, 1 nets, and 50 connections (7.61% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------