71001181
Warning
0
51001046
Warning
button
35002000
Info
35921504
Info
C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1
35921012
Info
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(16):
displaydriverwdecoder_top
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd
16
35921010
Info
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(50):
arch
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd
50
35921012
Info
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15):
displaydriverwrapper
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd
15
35921010
Info
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(35):
arch
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd
35
35921205
Warning
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(31):
DisplayDriverWrapper
arch
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd
31
35001611
Warning
1166052
Warning
logical
clk
clk
1166064
Warning
input
clk
1166052
Warning
logical
reset
reset
1166064
Warning
input
reset
1166052
Warning
logical
button
button
1166064
Warning
input
button
1163101
Warning
6
60001135
Info
1166052
Warning
logical
button
button
1163101
Warning
1
2011000
Info
2019991
Warning
CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
CD638
C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd
38
11
38
15
Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
2019991
Warning
MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
MT529
c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd
76
8
76
9
Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
2019993
Warning
MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
MT420
Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"