C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synlog\DisplayDriverwDecoder_impl1_fpga_mapper.srr
START OF TIMING REPORT
Clock Name
Req Freq
Est Freq
Slack
display_driver_wrapper|clk
433.9 MHz
368.8 MHz
-0.407