Synthesis and Ngdbuild Report
synthesis: version Diamond (64-bit) 3.8.0.115.3
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Sun Jan 08 00:19:59 2017
Command Line: synthesis -f DisplayDriverwDecoder_impl1_lattice.synproj -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml
Synthesis options:
The -a option is ECP5U.
The -s option is 6.
The -t option is CABGA381.
The -d option is LFE5U-45F.
Using package CABGA381.
Using performance grade 6.
##########################################################
### Lattice Family : ECP5U
### Device : LFE5U-45F
### Package : CABGA381
### Speed : 6
##########################################################
Optimization goal = Timing
Top-level module name = DisplayDriverWrapper.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/lscc/diamond/3.8_x64/ispfpga/sa5p00/data (searchpath added)
-p C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1 (searchpath added)
-p C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build (searchpath added)
VHDL library = work
VHDL design file = C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd
VHDL design file = C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd
NGD file = DisplayDriverwDecoder_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v. VERI-1482
Compile design.
Compile Design Begin
INFO - synthesis: The default VHDL library search path is now "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1". VHDL-1504
Analyzing VHDL file c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd. VHDL-1481
INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(16): analyzing entity displaydriverwdecoder_top. VHDL-1012
INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(50): analyzing architecture arch. VHDL-1010
unit DisplayDriverWrapper is not yet analyzed. VHDL-1485
Analyzing VHDL file c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd. VHDL-1481
INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15): analyzing entity displaydriverwrapper. VHDL-1012
INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(35): analyzing architecture arch. VHDL-1010
unit DisplayDriverWrapper is not yet analyzed. VHDL-1485
unit DisplayDriverWrapper is not yet analyzed. VHDL-1485
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15): executing DisplayDriverWrapper(arch)
WARNING - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(31): replacing existing netlist DisplayDriverWrapper(arch). VHDL-1205
Top module name (VHDL): DisplayDriverWrapper
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/sa5p00/data/sa5plib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'sa5p45.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status: Final Version 1.38.
Top-level module name = DisplayDriverWrapper.
######## Missing driver on net disp_data[13]. Patching with GND.
######## Missing driver on net disp_data[12]. Patching with GND.
######## Missing driver on net disp_data[11]. Patching with GND.
######## Missing driver on net disp_data[10]. Patching with GND.
######## Missing driver on net disp_data[9]. Patching with GND.
######## Missing driver on net disp_data[8]. Patching with GND.
######## Missing driver on net disp_data[7]. Patching with GND.
######## Missing driver on net disp_data[6]. Patching with GND.
######## Missing driver on net disp_data[5]. Patching with GND.
######## Missing driver on net disp_data[4]. Patching with GND.
######## Missing driver on net disp_data[3]. Patching with GND.
######## Missing driver on net disp_data[2]. Patching with GND.
######## Missing driver on net disp_data[1]. Patching with GND.
######## Missing driver on net disp_data[0]. Patching with GND.
GSR will not be inferred because no asynchronous signal was found in the netlist.
Applying 1.000000 MHz constraint to all clocks
WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in DisplayDriverWrapper_drc.log.
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/sa5p00/data/sa5plib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
WARNING - synthesis: logical net 'clk' has no load.
WARNING - synthesis: input pad net 'clk' has no legal load.
WARNING - synthesis: logical net 'reset' has no load.
WARNING - synthesis: input pad net 'reset' has no legal load.
WARNING - synthesis: logical net 'button' has no load.
WARNING - synthesis: input pad net 'button' has no legal load.
WARNING - synthesis: DRC complete with 6 warnings.
All blocks are expanded and NGD expansion is successful.
Writing NGD file DisplayDriverwDecoder_impl1.ngd.
################### Begin Area Report (DisplayDriverWrapper)######################
Number of register bits => 0 of 44457 (0 % )
GSR => 1
OB => 15
################### End Area Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 0
Clock Enable Nets
Number of Clock Enables: 0
Top 0 highest fanout Clock Enables:
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : disp_data[0], loads : 0
Net : disp_data[1], loads : 0
Net : disp_data[2], loads : 0
Net : disp_data[3], loads : 0
Net : disp_data[4], loads : 0
Net : disp_data[5], loads : 0
Net : disp_data[6], loads : 0
Net : disp_data[7], loads : 0
Net : disp_data[8], loads : 0
Net : disp_data[9], loads : 0
################### End Clock Report ##################
Peak Memory Usage: 99.668 MB
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Elapsed CPU time for LSE flow : 1.156 secs
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