#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016 #install: C:\lscc\diamond\3.8_x64\synpbase #OS: Windows 8 6.2 #Hostname: DESKTOP-1AUKF7V # Sun Jan 08 00:49:32 2017 #Implementation: impl1 Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : DisplayDriverWrapper.vhd(15) | Top entity is set to DisplayDriverWrapper. File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling VHDL syntax check successful! File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling @N:CD630 : DisplayDriverWrapper.vhd(15) | Synthesizing work.displaydriverwrapper.arch. @W:CD638 : DisplayDriverWrapper.vhd(38) | Signal empty is undriven. Either assign the signal a value or remove the signal declaration. @N:CD630 : DisplayDriverwDecoder_Top.vhd(16) | Synthesizing work.displaydriverwdecoder_top.arch. Post processing for work.displaydriverwdecoder_top.arch @W:CL240 : DisplayDriverwDecoder_Top.vhd(38) | disp_data is not assigned a value (floating) -- simulation mismatch possible. Post processing for work.displaydriverwrapper.arch @N:CL159 : DisplayDriverWrapper.vhd(20) | Input button is unused. At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sun Jan 08 00:49:32 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 @N: : | Running in 64-bit mode File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling @N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level @N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sun Jan 08 00:49:32 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sun Jan 08 00:49:32 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016 @N: : | Running in 64-bit mode File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling @N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level @N:NF107 : DisplayDriverWrapper.vhd(15) | Selected library: work cell: DisplayDriverWrapper view arch as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sun Jan 08 00:49:34 2017 ###########################################################] Pre-mapping Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.03L-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A:MF827 : | No constraint file specified. Linked File: impl1_scck.rpt Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB) ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------------------- DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8 ===================================================================================================== @W:MT529 : displaydriverwdecoder_top.vhd(75) | Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. Finished Pre Mapping Phase. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) None None Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Jan 08 00:49:34 2017 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.03L-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ============================== Non-Gated/Non-Generated Clocks =============================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------- ClockId0001 clk port 8 DDwD_Top.ascii_reg[6] ============================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB) Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi L-2016.03L-1 @N:BW106 : | Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB) Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) @W:MT420 : | Found inferred clock DisplayDriverWrapper|clk with period 0.77ns. Please declare a user-defined clock on object "p:clk" ##### START OF TIMING REPORT #####[ # Timing Report written on Sun Jan 08 00:49:36 2017 # Top view: DisplayDriverWrapper Requested Frequency: 1297.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -0.136 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------ DisplayDriverWrapper|clk 1297.0 MHz 1102.5 MHz 0.771 0.907 -0.136 inferred Autoconstr_clkgroup_0 ==================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------- DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.771 -0.136 | No paths - | No paths - | No paths - =========================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: DisplayDriverWrapper|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------- DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.853 -0.136 DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.853 -0.136 DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.853 -0.136 DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.853 -0.136 DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.853 -0.136 DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.853 -0.136 DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.853 -0.136 DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.853 -0.136 ============================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------- DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.717 -0.136 DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.717 -0.136 DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.717 -0.136 DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.717 -0.136 DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.717 -0.136 DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.717 -0.136 DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.717 -0.136 DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.717 -0.136 =============================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 0.771 - Setup time: 0.054 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.717 - Propagation time: 0.853 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.136 Number of logic level(s): 0 Starting point: DDwD_Top.ascii_reg[0] / Q Ending point: DDwD_Top.ascii_reg[0] / D The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.853 0.853 - ascii_reg[0] Net - - - - 1 DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.853 - ======================================================================================= Path information for path number 2: Requested Period: 0.771 - Setup time: 0.054 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.717 - Propagation time: 0.853 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.136 Number of logic level(s): 0 Starting point: DDwD_Top.ascii_reg[1] / Q Ending point: DDwD_Top.ascii_reg[1] / D The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.853 0.853 - ascii_reg[1] Net - - - - 1 DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.853 - ======================================================================================= Path information for path number 3: Requested Period: 0.771 - Setup time: 0.054 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.717 - Propagation time: 0.853 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.136 Number of logic level(s): 0 Starting point: DDwD_Top.ascii_reg[2] / Q Ending point: DDwD_Top.ascii_reg[2] / D The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.853 0.853 - ascii_reg[2] Net - - - - 1 DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.853 - ======================================================================================= Path information for path number 4: Requested Period: 0.771 - Setup time: 0.054 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.717 - Propagation time: 0.853 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.136 Number of logic level(s): 0 Starting point: DDwD_Top.ascii_reg[3] / Q Ending point: DDwD_Top.ascii_reg[3] / D The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.853 0.853 - ascii_reg[3] Net - - - - 1 DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.853 - ======================================================================================= Path information for path number 5: Requested Period: 0.771 - Setup time: 0.054 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.717 - Propagation time: 0.853 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.136 Number of logic level(s): 0 Starting point: DDwD_Top.ascii_reg[4] / Q Ending point: DDwD_Top.ascii_reg[4] / D The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.853 0.853 - ascii_reg[4] Net - - - - 1 DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.853 - ======================================================================================= ##### END OF TIMING REPORT #####] Constraints that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) --------------------------------------- Resource Usage Report Part: lfe5u_45f-6 Register bits: 8 of 43848 (0%) PIC Latch: 0 I/O cells: 17 Details: FD1S3IX: 5 FD1S3JX: 3 GSR: 1 IB: 2 OB: 15 PUR: 1 VHI: 2 VLO: 1 false: 1 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Jan 08 00:49:36 2017 ###########################################################]