| Project Settings |
|---|
| Project Name | impl1_syn | Implementation Name | impl1 |
| Top Module | [auto] | Pipelining | 1 |
| Retiming | 0 | Resource Sharing | 1 |
| Fanout Guide | 100 | Disable I/O Insertion | 0 |
| Disable Sequential Optimizations | 0 | Clock Conversion | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
15 |
1 |
0 |
- |
0m:00s |
- |
17-Jan-17
01:29:36 |
| (premap) | Complete |
2 |
1 |
0 |
0m:00s |
0m:00s |
142MB |
17-Jan-17
01:29:38 |
| (fpga_mapper) | Complete |
11 |
1 |
0 |
0m:01s |
0m:01s |
145MB |
17-Jan-17
01:29:40 |
| Multi-srs Generator |
Complete | | | | | | | 17-Jan-17
01:29:37 |
| Area Summary |
|---|
|
| Register bits | 13 |
I/O cells | 19 |
| Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
| ORCA LUTs
(total_luts) | 4 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| DisplayDriverWrapper|clk | 433.9 MHz | 368.8 MHz | -0.407 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 0 |
| |
|