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-- Entity: ascii_decoder
-- Date:2017-01-07  
-- Author: GL     
--
-- Description: 
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--! @file
--! @brief ASCII decoding table with I/O control logic
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ascii_decoder is
	port  (
        clk     : in    std_logic;                                      --! input clock, xx MHz.
        reset   : in    std_logic;
        
        --! ascii_in(7) represents the DP state so it is not decoded. 
        --! Symbol codes from 0x00 to 0x7F are without DP lit. Symbol codes from 0x80 to 0xFF have DP lit.
        ascii_in: in    std_logic_vector(7 downto 0);                   --! input ascii code to be displayed

        disp_data_q : out std_logic_vector(14 downto 0)                 --! decoded ascii code output with symbol bit map
	);
end ascii_decoder;

architecture arch of ascii_decoder is

    --! Q represents the symbol's bit mapping overlay over the 14-segment display.
    signal Q : std_logic_vector(13 downto 0);
begin

--! @brief Decoding table handling all symbols except the DP
rom_decoding_table: entity work.decoder_table_dist_rom
port map(
    Address => ascii_in(6 downto 0),
    Q       => Q
);

--! Inversion of ascii_in(7) is needed as '0' is display segment active level
disp_data_q <= (not ascii_in(7)) & Q;                                     


end arch;