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# clock pin for Nexys 2 Board
NET "A_CLK"   LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
NET "B_CLK"   LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1

# 7 segment display
NET "SEG<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
NET "SEG<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
NET "SEG<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
NET "SEG<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
NET "SEG<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
NET "SEG<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
NET "SEG<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
NET "DP"     LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP

NET "AN<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
NET "AN<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
NET "AN<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
NET "AN<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3

# Leds
NET "LED<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
NET "LED<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
NET "LED<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
NET "LED<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
NET "LED<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
NET "LED<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
NET "LED<6>" LOC = "E4";  # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
NET "LED<7>" LOC = "P4";  # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500

# Switches
NET "SW<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
NET "SW<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
NET "SW<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
NET "SW<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
NET "SW<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
NET "SW<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
NET "SW<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
NET "SW<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7

# Buttons

NET "BTN<0>" LOC = "B18";     # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
NET "BTN<1>" LOC = "D18";     # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
NET "BTN<2>" LOC = "E18";     # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
NET "BTN<3>" LOC = "H13";     # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3

# VGA Connector 
NET "VGARED<0>"   LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
NET "VGARED<1>"   LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
NET "VGARED<2>"   LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
NET "VGAGREEN<0>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
NET "VGAGREEN<1>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
NET "VGAGREEN<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
NET "VGABLUE<0>"  LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
NET "VGABLUE<1>"  LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2

NET "HSYNC_N" LOC = "T4";       # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
NET "VSYNC_N" LOC = "U3";       # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC

# PS/2 connector
NET "PS2C" LOC = "R12";       # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
NET "PS2D" LOC = "P11";       # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D







# 12 pin connectors
NET "JA_1" LOC = "L15";      # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
NET "JA_2" LOC = "K12";      # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
NET "JA_3" LOC = "L17";      # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
NET "JA_4" LOC = "M15";      # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
NET "JA_7" LOC = "K13";      # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
NET "JA_8" LOC = "L16";      # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
NET "JA_9" LOC = "M14";      # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
NET "JA_10" LOC = "M16";     # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
NET "JB_1" LOC = "M13";      # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
NET "JB_2" LOC = "R18";      # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
NET "JB_3" LOC = "R15";      # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
NET "JB_4" LOC = "T17";      # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
NET "JB_7" LOC = "P17";      # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
NET "JB_8" LOC = "R16";      # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
NET "JB_9" LOC = "T18";      # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
NET "JB_10" LOC = "U18";      # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
NET "JC_1" LOC = "G15";      # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
NET "JC_2" LOC = "J16";      # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
NET "JC_3" LOC = "G13";      # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
NET "JC_4" LOC = "H16";      # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
NET "JC_7" LOC = "H15";      # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
NET "JC_8" LOC = "F14";      # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
NET "JC_9" LOC = "G16";      # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
NET "JC_10" LOC = "J12";      # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10


NET "RTS" LOC = "J13";      # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
NET "CTS" LOC = "M18";      # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
NET "RXD" LOC = "N18";      # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
NET "TXD" LOC = "P18";      # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4


# RS232 connector
NET "RS_RX" LOC = "U6";        # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
NET "RS_TX" LOC = "P9";        # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX




# onBoard Cellular RAM and StrataFlash
NET "MEMOE"     LOC = "T2";  # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
NET "MEMWR"     LOC = "N7";  # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE

NET "RAMADV"    LOC = "J4";  # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
NET "RAMCS"     LOC = "R6";  # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
NET "RAMCLK"    LOC = "H5";  # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
NET "RAMCRE"    LOC = "P7";  # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
NET "RAMLB"     LOC = "K5";  # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
NET "RAMUB"     LOC = "K4";  # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
NET "RAMWAIT"   LOC = "F5";  # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT

NET "FLASHRP"    LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
NET "FLASHCS"    LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
NET "FLASHSTSTS" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS

NET "MEMADR<1>"  LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
NET "MEMADR<2>"  LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
NET "MEMADR<3>"  LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
NET "MEMADR<4>"  LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
NET "MEMADR<5>"  LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
NET "MEMADR<6>"  LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
NET "MEMADR<7>"  LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
NET "MEMADR<8>"  LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
NET "MEMADR<9>"  LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
NET "MEMADR<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
NET "MEMADR<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
NET "MEMADR<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
NET "MEMADR<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
NET "MEMADR<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
NET "MEMADR<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
NET "MEMADR<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
NET "MEMADR<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
NET "MEMADR<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
NET "MEMADR<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
NET "MEMADR<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
NET "MEMADR<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
NET "MEMADR<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
NET "MEMADR<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23

NET "MEMDB<0>"  LOC = "L1";  # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
NET "MEMDB<1>"  LOC = "L4";  # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
NET "MEMDB<2>"  LOC = "L6";  # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
NET "MEMDB<3>"  LOC = "M4";  # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
NET "MEMDB<4>"  LOC = "N5";  # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
NET "MEMDB<5>"  LOC = "P1";  # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
NET "MEMDB<6>"  LOC = "P2";  # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
NET "MEMDB<7>"  LOC = "R2";  # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
NET "MEMDB<8>"  LOC = "L3";  # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
NET "MEMDB<9>"  LOC = "L5";  # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
NET "MEMDB<10>" LOC = "M3";  # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
NET "MEMDB<11>" LOC = "M6";  # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
NET "MEMDB<12>" LOC = "L2";  # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
NET "MEMDB<13>" LOC = "N4";  # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
NET "MEMDB<14>" LOC = "R3";  # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
NET "MEMDB<15>" LOC = "T1";  # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15



# onBoard USB controller
NET "EPPASTB"   LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
NET "EPPDSTB"   LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
NET "EPPWAIT"   LOC = "N9";  # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
NET "EPPDB<0>"  LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
NET "EPPDB<1>"  LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
NET "EPPDB<2>"  LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
NET "EPPDB<3>"  LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
NET "EPPDB<4>"  LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
NET "EPPDB<5>"  LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
NET "EPPDB<6>"  LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
NET "EPPDB<7>"  LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7


# FX2 connector
NET "PIO<0>"  LOC = "B4";  # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
NET "PIO<1>"  LOC = "A4";  # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
NET "PIO<2>"  LOC = "C3";  # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
NET "PIO<3>"  LOC = "C4";  # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
NET "PIO<4>"  LOC = "B6";  # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
NET "PIO<5>"  LOC = "D5";  # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
NET "PIO<6>"  LOC = "C5";  # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
NET "PIO<7>"  LOC = "F7";  # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
NET "PIO<8>"  LOC = "E7";  # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
NET "PIO<9>"  LOC = "A6";  # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
NET "PIO<10>" LOC = "C7";  # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
NET "PIO<11>" LOC = "F8";  # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
NET "PIO<12>" LOC = "D7";  # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
NET "PIO<13>" LOC = "E8";  # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
NET "PIO<14>" LOC = "E9";  # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
NET "PIO<15>" LOC = "C9";  # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
NET "PIO<16>" LOC = "A8";  # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
NET "PIO<17>" LOC = "G9";  # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
NET "PIO<18>" LOC = "F9";  # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40


# This file is a general .ucf for Nexys2 rev A board
# To use it in a project:
# - remove or comment the lines corresponding to unused pins
# - rename the used signals according to the project

# Both versions are provided in this file.
# Keep only the appropriate one, and remove or comment the other one.





NET "USBCLK"    LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
NET "USBOE"     LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
NET "USBWR"     LOC = "V9";  # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SWLR
NET "USBPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
NET "USBDIR"    LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
NET "USBMODE"   LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
NET "USBADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
NET "USBADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
#NET "USBRDY"   LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
NET "USBFLAG"   LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC