# Copyright 2013, Sinclair R.F., Inc.
# Test bench for synthesis tools:  combine INSTRUCTION and DATA_STACK
#
# Minimum Logic utilization
#   Xilinx      XC3S50A         N/A -- Spartan 3A doesn't support asynchronous reads
#   Xilinx      XC6SLX4         33 Slices, 111 Slice LUTs

ARCHITECTURE core/9x8 Verilog

INSTRUCTION     1024
DATA_STACK      16
RETURN_STACK    16
COMBINE         INSTRUCTION,DATA_STACK

OUTPORT 1-bit o_led O_LED

ASSEMBLY        uc_led.s