#
# Copyright 2012, Sinclair R.F., Inc.
#
# Test bench for open_drain peripheral.
#

ARCHITECTURE    core/9x8 Verilog
INSTRUCTION     64
DATA_STACK      32
RETURN_STACK    16

OUTPORT         1-bit           o_env           O_ENV

PERIPHERAL      open_drain      inport=I_OD \
                                outport=O_OD \
                                iosignal=io_od \
                                @WIDTH@

ASSEMBLY tb_open_drain.s