#
# Copyright 2013-2014, Sinclair R.F., Inc.
#
# Test bench for outFIFO_async peripheral.
#

ARCHITECTURE    core/9x8 Verilog
INSTRUCTION     128
DATA_STACK      64
RETURN_STACK    16

PORTCOMMENT     asynchronous output FIFO
PERIPHERAL      outFIFO_async   outclk=i_aclk           \
                                data=o_data             \
                                data_rd=i_data_rd       \
                                data_empty=o_data_empty \
                                outport=O_DATA          \
                                infull=I_FULL           \
                                depth=32

PORTCOMMENT     feed-back empty condition
INPORT          1-bit           i_empty                 I_EMPTY

PORTCOMMENT     termination signal
OUTPORT         1-bit           o_done                  O_DONE

ASSEMBLY tb_outFIFO_async.s