BUGS:

  example
*   "<", ... operators for signed 8-bit values

  ssbcc
*   change "outstatus" to "outfull" for UART and UART_Tx
*   add size[variable_name]
    add r* to over-write either s_T or s_N?
*   accommodate Lattice Diamond synthesis and memory initialization
*   make "quiet" the default
*   ensure timer tolerance is non-zero
*   ensure all "raise" statements include the source line code number
*   write COMBINE MEMORY tests
?   bit-slice constants (similarly to parameters)
    handle ';' that aren't preceded by a space
    use .IFNDEF instead of checking assembler check for previously included files
    add "rot" instruction?
    add address range validation for memory accesses
    add warning for unreachable code following .jump or .return instructions
    add "share memory" feature?
      for dual-port memories in slave peripherals (i.e., registers readable by the bus master)
      for peripherals such as adders where long chains of outputs and inports would have been required and .store+/- and .fetch+/- would be much more efficient code-wise
      how to accommodate multiple "shared memory" peripherals?
    remove dead parameters and dead code
    rework design as required to make it more robust
    documentation
      top-level overview, point to implemented cores
      required:  ARCHITECTURE and sizes, ASSEMBLY, and HDL
      I/O Ports
      INPORT and OUTPORT
      PERIPHERAL
        finish doc/peripheral.html
*     all error messages
    generate Altera SOPC/Qsys TCL script
    add VHDL

  core/9x8
    documentation
      update
      assembler
        directives
        instructions
          change "opcodes.html" to "instructions.html", ...
        parameters
        constants
      peripherals
      running the test benches
    core.v
      additional instructions?
        "invert" opcode in 6'b000100 group
        "tst&=" and "tst&<>" instructions -- replace T with the stated comparison based on the bitwise and of T and N
        "cmp=" and "cmp<>" instructions -- replace T with the statued comparison based on N-T
    asm
      require .memory directive to be repeated after other directives, EOF, etc.
      improve error message for missing input files
      add non-return-stack-alteration restriction to some optional macro arguments
      implement .abbr directive
      add .if(...) [.elif(...)]* [.else] .endif directive set
        avoid full parsing of false branches (accommodate other cores?)
        add symbol for current core -- is9x8 (?)
    peripherals
      multi-byte adder
      multiplier
      PICK -- emulate the Forth operator?
        this can be done if the data stack is in its own dual-port memory, but that kinds of defeats the purpose of a small micro controller
      bus slave peripherals -- store external commands in a FIFO and statuses in dual-port RAM or shared RAM for external reads
        SPI_slave
        I2C_slave
      SoC Interconnects
        wishbone_slave
        avalon_slave
        wishbone_master
        avalon_master
        ARM_slave
    core.vhd
      do this once core.v is completed

  examples
*   Game-of-life
    add more examples
      "echo" program
      Jim Haberly -- accumulate 10 samples from an ADC
    JPEG compression example?
      Cast's JPEG-E core: http://www.cast-inc.com/ip-cores/images/jpeg-e/index.html (1343 slices, 170 MHz, 7 RAMB16, 9 DSP48)

  lib/9x8/math.s
    -- incorporate adder peripheral
    -- add_u8_u32__u32, ...
    -- sub_uX_uY__uZ, X,Y,Z \in {8,16,24,32}, Z \in min(X,Y)+{0,8}, Z<=32
    -- add signed versions

  lib/9x8/forth.s
    -- identify good instructions to include
      pick

  publicize
    - opencores
    - ssbcc.net
    - Programmable Planet
    - EETimes and other e-rags
    - add to web page