Subversion Repositories turbo8051

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 132 02/25/2009 SJ Full Version
# Date created = 16:06:19  March 15, 2011
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#               turbo8051_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#               assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C15AF484A7
set_global_assignment -name TOP_LEVEL_ENTITY turbo8051
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:06:19  MARCH 15, 2011"
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga

set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125

set_global_assignment -name SEARCH_PATH ../../rtl/lib
set_global_assignment -name SEARCH_PATH ../../rtl/8051

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name VERILOG_FILE ../../models/altera/altera_stargate_pll.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_wr_mem2mem.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/clk_ctl.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/dble_reg.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/double_sync_high.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/double_sync_low.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/dpath_ctrl.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/registers.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/sfifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/stat_counter.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/toggle_sync.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_crossbar.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_interface.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_rd_mem2mem.v
set_global_assignment -name VERILOG_FILE ../../rtl/lib/async_fifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/core/core.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/top/g_mac_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_tx_fsm.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_deferral.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_tx_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_rx_fsm.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_cfg_mgmt.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/s2f_sync.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_md_intf.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_ad_fltr.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_deferral_rx.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_rx_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_mii_intf.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_mac_core.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/crc32/g_rx_crc32.v
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/crc32/g_tx_crc32.v
set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_core.v
set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_ctl.v
set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_if.v
set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_cfg.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_rxfsm.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_txfsm.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_core.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_cfg.v
set_global_assignment -name VERILOG_FILE ../../rtl/clkgen/clkgen.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_alu_src_sel.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_alu.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_decoder.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_divide.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_multiply.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_memory_interface.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_ram_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_acc.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_comp.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_sp.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_dptr.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_cy_select.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_psw.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_indi_addr.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_ports.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_b_register.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_uart.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_int.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_tc.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_tc2.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_sfr.v
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_ram_256x8_two_bist.v
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF