Versatile FIFO
A versatile FIFO supporting both sync and async implementations with multiple parallell channels
Brought to You By ORSoC / OpenCores

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Table of Contents

Chapter 1 Introduction	4

Asynchronous FIFO implementation	4

Synchronous FIFO implementation	4

Multiple FIFO implementation	5

Chapter 2 FIFO building blocks	6

Dual port memory	6

Single clock dual port RAM	6

Single clock true dual port RAM	6

Dual clock dual port RAM	7

Dual clock tue dual port RAM	7

Recommended Resources	9

Chapter 1 Introduction

The FIFO implementation outlined in this document can easily be configured to suit the following

asynchronous FIFO with different clock domains for read and write sides

synchronous FIFO with programmable flags

multiple FIFO sharing the same memory resource

Asynchronous FIFO implementation

This configuration uses gray counter as FIFO pointers and an asynchronous compare function. The read and write pointers are within different clock domains. To be able to have glitch free compare function it is important that the pointers are clocked signals and that no more than one signal can change its value on any clock signal.

For read and write pointers use "Versatile counter" found at OpenCores. Configured as gray counter.

This FIFO has one clock domain for the write side and an other for the read side.

Synchronous FIFO implementation

For minimal area and highest performance this implementation uses linear feedback shift registers, LFSR, as memory pointers. The logic generating FIFO flags could either be a compare function based on q_next from address counters or based on an up/down counter keeping track of number of data words in memory.

For read and write pointers use "Versatile counter" found at OpenCores. Configured as LFSR counter. This applies also to FIFO content counter.

This FIFO has one clock domain for the write side and the read side.

Multiple FIFO implementation

In some cases more than one FIFO can share the same memory. This makes better use of the FPGA resources. Most FPGA has built-in memories with 4 kbits to 8 kbits. These memories can in many cases be configured as true dual port memories, that is with read and write possibilities on both sides.

This is the case for the following FPGA families

ACTEL ProASIC3

ALTERA Cyclone III

Many application have one wishbone interface and many FIFO channels with different type of real time data. In this case only one FIFO can be written to from the system bus side meaning that there is no problem sharing the dual port memory.

An example of a system that can use this type of implementation is a system with an interface towards an external AC´97 compatible audio codec. The external interface is a bit stream with audio data. System bus interface could have 6 FIFO channels (for 5.1 audio support). From the system side there will be 6 individual FIFO queues. Internally all queues can share one memory instance. A FSM will read out audio data from the FIFO sequentially.

Chapter 2 FIFO building blocks

All FIFO implementations are based on the following building blocks. Each block is available as a Verilog RTL module.

dual port memory

read and write pointers

logic generating FIFO empty and FIFO full and optionally other FIFO flags

optional multiplexer used for multiple FIFO queues sharing a common memory

From this a large number of different FIFO can be constructed. Pick your bricks

Dual port memory

There are a few variants of the dual port memory implementations. The memory could have read/write support on both sides (true dual port) or have one read and one write side. Also there can be individual clock signals for read or write.

Single clock dual port RAM

A dual port memory with one write side and one read side with one common read and write clock.

Single clock dual port RAM
Filename	versatile_fifo_dual_port_ram_sc_1w.v
Module name	versatile_fifo_dual_port_ram_sc_1w
Parameters	default value
DATA_WIDTH	8
ADDR_WIDTH	9
A side
d_a	input
adr_a	input
we_a	input
B side
q_b	output
adr_b	output
common
clk	input

Single clock true dual port RAM

A dual port memory with two read/write sides with one common clock.

Single clock dual port RAM
Filename	versatile_fifo_dual_port_ram_sc_1w.v
Module name	versatile_fifo_dual_port_ram_sc_1w
Parameters	default value
DATA_WIDTH	8
ADDR_WIDTH	9
A side
d_a	input
q_a	output
adr_a	input
we_a	input
B side
d_a	input
q_b	output
adr_b	output
we_b	input
common
clk	input

Dual clock dual port RAM

A dual port memory with one write side and one read side with individual read and write clock.

Single clock dual port RAM
Filename	versatile_fifo_dual_port_ram_sc_1w.v
Module name	versatile_fifo_dual_port_ram_sc_1w
Parameters	default value
DATA_WIDTH	8
ADDR_WIDTH	9
A side
d_a	input
adr_a	input
we_a	input
clk_a	input
B side
q_b	output
adr_b	output
clk_b	input

Dual clock true dual port RAM

A dual port memory with two read/write sides with individual clocks.

Single clock dual port RAM
Filename	versatile_fifo_dual_port_ram_sc_1w.v
Module name	versatile_fifo_dual_port_ram_sc_1w
Parameters	default value
DATA_WIDTH	8
ADDR_WIDTH	9
A side
d_a	input
q_a	output
adr_a	input
we_a	input
clk_a	input
B side
d_a	input
q_b	output
adr_b	output
we_b	input
clk_b	input

Recommended Resources

ORSoC – http://www.orsoc.se

ORSoC is a fabless ASIC design & manufacturing services company, providing RTL to ASIC design services and silicon fabrication service. ORSoC are specialists building complex system based on the OpenRISC processor platform.

Open Source IP – http://www.opencores.org

Your number one source for open source IP and other FPGA/ASIC related information.