Versatile library
A collection of frequently used modules with synthesis support
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Table of Contents

Description	4

Clock and reset	5

vl_gbuf	5

vl_sync_reset	5

vl_pll	5

Simulation model	5

Registers	7

Dff	7

dff_ce	7

dff_sr	7

Appendix A
vl_pll usage example with ACTEL ProASIC3 target	8

Recommended Resources	9

Description

A Verilog HDL library with frequently used functions.

Care have been taken to fully support synthesis of all modules. Different versions exist for optimal synthesis support. Currently ACTEL and ALTERA are supported

The following types of functions are included

Clock and reset
Global buffers, PLL and sync reset

Registers
with clock enable, async set and reset, …

Counters
Binary, Gray, LFSR

Memories
RAM, dual port RAM, …

Wishbone
Wishbone system-on-chip bus realted logic

Most modules uses parameter for per instance uniqeness.

Different version of the library exist. All included module names are identical in all library versions. Retargeting a design can be to use a different library.

versatile_library.v
Target independent library

versatile_library_actel.v
ACTEL version with synthesis constraints for synplify / Libero

versatile_library_altera.v
ALTERA version with synthesis constraints for QuartusII

Note: The target independent could also be used with target specific constarints simply by adding the following switch during simulation and or synthesis

+define+ACTEL or
+define+ALTERA

Clock and reset

vl_gbuf

A global buffer to be used to ensure global routing resources for high fanout signals such as clock and reset networks.

Signal	Direction	Comment
i	Input
o	Output	Global signal

vl_sync_reset

To ensure proper startup behaviour each clock network should have a dedicated synchronous reset signal.

Signal	Direction	Comment
rst_n_i	Input	Async active low reset input, normally driver from external reset and/or PLL lock signal
rst_o	Input	Global synchronous reset signal, active high
clk	Clock source

vl_pll

Most FPGA have PLL functions built-in. This function is one of few which are not possible to describe in HDL and have synthesis support. A functional model can be described.

This library contains the following:

vl_pll in versatile_library.v
a functional model for simulation only

vl_pll in versatileLibrary_actel.v
a wrapper for one or more actual PLL
a functional model for simulation only
the later used if define SIM_PLL is applied at simulation time

Simulation model

Parameters

Parameter	Default value	Comment
index	0	Only used for synthesis. Parameter used in PLL wrapper to give a unique name to actual PLL. Parameter is concateneted with pll to give actual name. Example: index=0 => instance name pll0
number_of_clocks	3	Defines number of generated clocks
clk_i_period_time	20	Defines input period time of input clock source, in ns
post_div[0:number_of_clocks-1]	[1,1,1]	Actual frequency of output clocks is frequency of clk_o[i] = 1/clk_i_period_time * mult[i] / div[i]
lock_delay	2000	Time to lock PLL, used in simulation only. Time in ns

Top level signals

Signal	Direction	Comment
clk_i	Input	Clock source
rst_n_i	Input	Async active low reset input used for synchronous reset generation
lock	Output	Signal indicating PLL is in locked state and that clock outputs are valid
clk_o [0:number_of_clocks-1]	Output	Vector with generated clocks

By specifying define SIM_PLL when cmpiling in simulator a functional model is used for PLL.

Appendix A have a detailed usage example of PLLs when used with ACTEL ProASIC3 as target.

Registers

Dff

dff_ce

dff_sr

Appendix A
vl_pll usage example with ACTEL ProASIC3 target

Requirements:

clk_i1 external clock, 66.666666667 MHz
shall generate
clk0 : 66.666666667 MHz
clk1 : 25.000 MHz
clk2 : 48 MHz

clk_i2 external 125.000 MHz
shall generate
clk3 : 125.000 MHz

each clock domain should have a global synchronised reset signal

Recommended Resources

ORSoC – http://www.orsoc.se

ORSoC is a fabless ASIC design & manufacturing services company, providing RTL to ASIC design services and silicon fabrication service. ORSoC are specialists building complex system based on the OpenRISC processor platform.

Open Source IP – http://www.opencores.org

Your number one source for open source IP and other FPGA/ASIC related information.