Wishbone B3 compatible SDRAM controller
A high performance SDRAM controller supporting SDR, DDR and DDR2 memories
Brought to You By ORSoC / OpenCores

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Table of Contents

Overall description	4

Wishbone interfaces	5

Supported wishbone bus cycles	5

Functional	6

TX FIFO	6

Chapter 2	7

TX FIFO buffer	7

RX FIFO buffer	7

Recommended Resources	9

Overall description

Overall goal of memory controller:

easily adaption to new memory types

multiple wishbone clock domains

multiple wishbone ports

FIFO interface towards memory interface

small footprint

This is a modular design with different wishbone interface modules.

Each module has two clock domains

wishbone clock domain

memory clock domain

Each module can support one or more wishbone ports. Each wishbone port can support different cycles.

An example of a wishbone interface module is the OR1200 wishbone interface module

Name	Read	write	Cti	Bte	comment
Instr	X	X	X	Instruction fetch
Data	X	X	X	X	Data read/write
Debug	X	X	Debug read/write

Wishbone interfaces

Supported wishbone bus cycles

This SDRAM controller uses two tag fields to effectively support burst transfer

CTI_I[2:0]	Description
000	Classic cycle
001	Constant address burst
010	Incrementing burst cycle
011	Reserved
100	Reserved
101	Reserved
110	Reserved
111	End-of-Burst

BTE_I[1:0]	Description
00	Linear burst
01	4-beat wrap burst
10	8-beat wrap burst
11	16-beat wrap burst

OR1200 wishbone interface

Port name	prio	Read	write	Cti	Bte	comment
Instr	1	X	X	X	Instruction fetch
Data	1	X	X	X	X	Data read/write
Debug	1	X	X	Debug read/write

Each port has priority one, sum of priorities is three. That means that out of three consecutive bus cycles each port will have at least one cycle.

For this small interface we will use three shift registers each with a three bit vector. Shift registers will be updated for each bus cycle.

Non used bus cycles will also update the shift registers.

The instruction and data port can use burst cycles.

FIFO depths:

Port name	Write FIFO depth	Read FIFO depth
Instr	16	16
Data	16	16
Debug	16	1

Functional

TX FIFO

address

{ adr_i[31:2], we_i, bte_i, cti_i }

data

{ dat[31:0], sel_i[3:0] }

Chapter 2

TX FIFO buffer

TX (outgoing) FIFO is used for transportation of address and data from wishbone bus to SDRAM.

Current design has 8 individual FIFO queues handling 8 wishbone interfaces.

Each FIFO is 36 bits wide x 32 words.

Each FIFO have FIFO empty and FIFO full flags.

signal	Width	direction	function
Write side
a_dat_i	32+4	Input	Write data to FIFO
a_we_i	1	Input	FIFO write enable
a_fifo_sel_i	3	Input	Select one of eight FIFO queues
a_fifo_full	8	Output	FIFO full
a_clk	1	Input	Wishbone clock
Read side
b_dat_o	32+4	Output	Read data from FIFO
b_we_i	1	Input	FIFO content modify
b_re_i	1	Input	FIFO read enable
b_fifo_sel_o	3	Input
b_fifo_empty	8	Output	FIFO empty
b_clk	1	Input	SDRAM clock

RX FIFO buffer

RX (incoming) FIFO is used for transportation of read data from SDRAM to wishbone bus.

PERL modules needed

cpan install Tie::Handle::CSV

cpan install Tie::CSV_File

Recommended Resources

ORSoC – http://www.orsoc.se

ORSoC is a fabless ASIC design & manufacturing services company, providing RTL to ASIC design services and silicon fabrication service. ORSoC are specialists building complex system based on the OpenRISC processor platform.

Open Source IP – http://www.opencores.org

Your number one source for open source IP and other FPGA/ASIC related information.