Wishbone B3 compatible SDRAM controller
A high performance SDRAM controller supporting SDR, DDR and DDR2 memories
Brought to You By ORSoC / OpenCores

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Table of Contents

Overall description	4

Wishbone interfaces	5

Supported wishbone bus cycles	5

Functional	6

TX FIFO	6

Chapter 2	7

TX FIFO buffer	7

RX FIFO buffer	7

Recommended Resources	9

Overall description

Overall goal of memory controller:

easily adaption to new memory types

multiple wishbone clock domains

multiple wishbone ports per clock domain

FIFO interface towards memory controller

balanced performance/are footprint

This a modular generic design. With parameter settings the number of ports, clock domains and SDRAM geometry configurations can be defined.

A module act as a interface towards the Wishbone system bus. This module has two clock domains

wishbone clock domain

memory clock domain

The memory clock domain is shared between all interface modules and the SDRAM memory. The wishbone clock domain could be unique for each interface.

Each module can support up to 16 wishbone ports. Each wishbone port can support different cycles.

To lower area usage each wishbone channel within one interface module share memory resources.

Wishbone cycles

Supported wishbone bus cycles

This SDRAM controller uses two tag fields to effectively support burst transfer

CTI_I[2:0]	Description
000	Classic cycle
001	Constant address burst
010	Incrementing burst cycle
011	Reserved
100	Reserved
101	Reserved
110	Reserved
111	End-of-Burst

BTE_I[1:0]	Description
00	Linear burst
01	4-beat wrap burst
10	8-beat wrap burst
11	16-beat wrap burst

Block diagram

The design is built with the following components

Top level with IO signals and parameters for configuration

Wishbone interface

ingress and egress async FIFOs shared between wishbone ports

logic to share FIFO resources

SDRAM controller

state machine generating SDRAM commands

versatile LFSR counter generating refresh request

logic to handle FIFO signals, including priorities between queues

delay line to correctly handle ingress FIFO in respect to SDRAM latency

Top level

Wishbone interface signals:

Signal	direction	comment
wb_adr_i_0	Input	Address input signals including cycle type as a concatenated vector
wb_dat_i_0	Input	Data and data strobe signals concatenated as a vector
wb_dat_o_0	Output	Data signals concatenated as a vector
wb_stb_i_0	Input	Wishbone strobe signals concatenated as a vector
wb_cyc_i_0	Input	Wishbone active cycle signals concatenated as a vector
wb_ack_o_0	Output	Wishbone acknowledge signals concatenated as a vector
wb_adr_i_1	Input	Address input signals including cycle type as a concatenated vector
wb_dat_i_1	Input	Data and data strobe signals concatenated as a vector
wb_dat_o_1	Output	Data signals concatenated as a vector
wb_stb_i_1	Input	Wishbone strobe signals concatenated as a vector
wb_cyc_i_1	Input	Wishbone active cycle signals concatenated as a vector
wb_ack_o_1	Output	Wishbone acknowledge signals concatenated as a vector
wb_adr_i_2	Input	Address input signals including cycle type as a concatenated vector
wb_dat_i_2	Input	Data and data strobe signals concatenated as a vector
wb_dat_o_2	Output	Data signals concatenated as a vector
wb_stb_i_2	Input	Wishbone strobe signals concatenated as a vector
wb_cyc_i_2	Input	Wishbone active cycle signals concatenated as a vector
wb_ack_o_2	Output	Wishbone acknowledge signals concatenated as a vector
wb_adr_i_3	Input	Address input signals including cycle type as a concatenated vector
wb_dat_i_3	Input	Data and data strobe signals concatenated as a vector
wb_dat_o_3	Output	Data signals concatenated as a vector
wb_stb_i_3	Input	Wishbone strobe signals concatenated as a vector
wb_cyc_i_3	Input	Wishbone active cycle signals concatenated as a vector
wb_ack_o_3	Output	Wishbone acknowledge signals concatenated as a vector
wb_clk	Input	Wishbone clock signals concatenated as a vector
wb_rst	Input	Wishbone reset signals concatenated as a vector

Independent of configuration all signals are always present. Dependent on configuration the vector length will vary.

Note also that “wb_adr_i_n” also contains cycle type information.

The “wb_adr_i_n” is defined as follows

{ adr_i[31:2], we_i, bte_i, cti_i }

Data vector going to SDRAM is defined as:

{ dat_i[31:0], sel_i[3:0] }

For data fetched from memory the following applies:

{ dat_o[31:0]}

The wishbone interface can be configured to suit the actual needs. This is done with a number parameters affecting the number of clock domains and the number of ports for each domain.

Parameter	Default value	Usage
nr_of_wb_clk_domains	1	Defines the actual number of clock domains used in the design
nr_of_wb_ports_clk0	1	Defines the number of ports for wishbone clock domain 0
nr_of_wb_ports_clk1	0	Defines the number of ports for wishbone clock domain 1
nr_of_wb_ports_clk2	0	Defines the number of ports for wishbone clock domain 2
nr_of_wb_ports_clk3	0	Defines the number of ports for wishbone clock domain 3

Non used clock domains could be set to any value but it will affect the length of the vector. Unused input signals should be connected to static signals. A defined value equal to zero will case a vector length of 2, any other value will lead to vector length equal to nr_of_wb_ports_clk_n times 36.

Additional parameters is used to configure the geometry of the SDRAM memories used.

Parameter	Default value	Usage
ba_size	2	For SDR type memories this should be set to 2
row_size	13	Depends on SDRAM
col_size	9	Depends on SDRAM
cl	3'b010	CAS latency. Valid values for SDR type memories is 3'b010 or 3'b011. This value affect both working mode of SDRAM and delay chains used in SDRAM controller.

Preprocessor defines can be used to chose type of SDRAM.

Current design support the following defines.

Parameter	Usage
SDR_16	SDR SDRAM with 16 bit databus
DDR_16	DDR SDRAM with 16 bit databus (work in progress)

For SDR_16 the following signals interfaces the SDRAM:

Signal	Width	Direction	Comment
ba_pad_o	1:0	Output	Bank address
a_pad_o	12:0	Output	Row/col address
ras_pad_o	1	Output	Row address strobe
cas_pad_o	1	Output	Column address strobe
we_pad_o	1	Output	Write enable
dqm_pad_o	1:0	Output	Data bus mask signals
dq_o	15:0	Output	Data bus output
dq_i	15:0	Input	Data bus input signals
dq_oe	1	Output	Data bus output enable
cke_pad_o	1	Output	Clock enable, in this design set to static 1
cs_n_pad_o	1	Output	Chip select, in this design set to static 0

Independent of memory type the following signals all always present:

Signal	Width	Direction	Comment
sdram_clk	1	Input	SDRAM clock domain clock signal
sdram_rst	1	Input	SDRAM clock domain reset signal

The sdram_clk signal should also be connected to the external SDRAM. For optimal IO timing an internal PLL should be used to ensure an internal and external sdram_clk with identical phase.

Wishbone interface

The wishbone interface module is built with three major parts

Ingress and egress FIFO queues

9 kbit asynchronous dual port memories configured as 256x36

FIFO gray address counters

asynchronous address compare for FIFO status

logic to prioritize among queues

logic to generate wishbone acknowledges signals

FIFO queues

The FIFO implementation is based on the versatile_fifo IP available from

http://www.opencores.org/project,versatile_fifo

which uses counter implementation from

http://www.opencores.org/project,versatile_counter

The FIFO address counter is defined in the spreadsheet versatile_counter.xls, sheet fifo_adr_counter

The depth of each FIFO is 16 words and the maximum numbers of FIFO queues is 16. Egress FIFO width is 36 and ingress 32.

Memory usage

egress queue : 16 queues x 16 words x 36 bits	= 9216 bits
ingress queue : 16 queues x 16 words x 32 bits	= 8192 bits

Queue priorities

Wishbone ports with lower port number have priority over ports with higher number.

Clock domains with higher number have priority over domains whith lower values.

Within one clock domain all ports are sharing one common egress memory. Only one wishbone port channel can write to this FIFO at any clock cycle.

Within one clock domain all ports are sharing one common ingress memory. Only one wishbone port can read out data at any clock cycle.

SDR 16 bit state machine

A controller for 16 bit wide SDR SDRAM memories is available.

The controller is made with the following resources

logic to handle FIFO read and write

FSM to generate control signals and SDRAM command and address

delay chain to handle ingress FIFO

FIFO control

The egress FIFOs has a number of status and control signals.

The egress FIFOs have one FIFO empty flag for each FIFO. The total number of empty flags is 16 queues x 4 clock domains. These flags are contained in a two dimensional array.

wire [0:15] fifo_empty[0:3];

Based on the rules for priorities between the wishbone channels an encoder is used to get a more condensed representation. A two bit field is used to select the clock domain with the non empty FIFO queue with the highest priority. A 16 bit vector is used to represent the queue with highest priority.

wire [0:15] fifo_sel_i;
wire [1:0] fifo_sel_domain_i;

Two modules, encode and decode, is used to changed between these two notations.

Refresh timer

A versatile counter configured as LFSR is used to generate refresh request.

Example

A memory (MT48LC16M16) requires 8192 refresh cycles every 64 ms. Providing an auto refresh command every 7.81 us ensures that each row is refreshed. For a sdram clock frequency of 125 MHz a refresh should be initiated every 976 cycle.

A cycle count of 976 requires a 10 bit counter. To get wrapping pattern:

./VersatileCounter.php 10 975
0110100001

FSM

A small state machine in combination with a 5 bit counter is used to generate SDRAM commands and row and column addresses.

State	Encoding	Functions
init	3'b000	Emits the follwong sequence of commands: precharge auto refresh auto refresh load mode register
idle	3'b001	Wait for refresh request or not FIFO empty condition Latch FIFO status signals
rfr	3'b010	Refresh, command sequence precharge (all banks) auto refresh
adr	3'b011	Latch ba, row, col, we, and bte (from FIFO)
pch	3'b100	Precharge current bank
act	3'b101	Activate row in current bank
rw	3'b111	Emit read, write or NOP (when FIFO is empty) Increments column address based on cycle type (bte)

Recommended Resources

ORSoC – http://www.orsoc.se

ORSoC is a fabless ASIC design & manufacturing services company, providing RTL to ASIC design services and silicon fabrication service. ORSoC are specialists building complex system based on the OpenRISC processor platform.

Open Source IP – http://www.opencores.org

Your number one source for open source IP and other FPGA/ASIC related information.