     [file version.texi not included]

This file documents the Versatile memory controller.

Copyright © 2011 ORSoC

     Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts.  A copy of the license is included in the section entitled ``GNU Free Documentation License''.

Scope of this Document
**********************

This document is the user guide for Versatile memory controller.

Introduction
************

This design implements a versatile memory controller. If used in combination with the versitale library, available from OpenCores, different types of system can easily be designed, including use cases where the system bus is in one clock domain and the memory controller in an other.

Block Diagram
*************

Clock domains
=============

Versatile memory controller contains the following clock domains

  * Wishbone slave clock domain

  * Wishbone master clock domain

  * RX GMII clock domain

  * TX GMII clock domain

Configuration registers
***********************

Register memory map
===================

Name   Address   Width   Access   Description
MODER   MODER   32   RW   Mode register
INT_SOURCE   INT_SOURCE   32   RW   Interrupt source register
INT_MASK   INT_MASK   32   RW   Interrupt mask register
TX_BD_NUM   TX_BD_NUM   32   RW   Transmit Buffer Descriptor number
MIIMODER   MIIMODER   32   RW   MII Mode Register
MIICOMMAND   MIICOMMAND   32   RW   MII Command Register
MIIADDRESS   MIIADDRESS   32   RW   MII Address Register
MIITX_DATA   MIITX_DATA   32   RW   MII Transmit Data
MIIRX_DATA   MIIRX_DATA   32   RW   MII Receive Data
MIISTATUS   MIISTATUS   32   RW   MII Status Register
MAC_ADDR0   MAC_ADDR0   32   RW   MAC address, LSB four bytes
MAC_ADDR1   MAC_ADDR1   32   RW   MAC address, MSB two bytes

MODER
-----

Bit   Access   Description
31-17     Reserved
16   RW   RECSMALL   Receive small packets
15   RW   PAD   Padding enabled
14   RW   HUGEN   Huge Packets Enable
13   RW   CRCEN   CRC enable
12-8      Reserved
7   RW   LOOPBCK   Loopback
6   RW   Resrved
5   RW   PRO   Promiscuous
4     Reserved
3   RW   BRO   Broadcast Address
2     Reserved
1   RW   TXEN   Transmit Enable
0   RW   RXEN   Receive Enable

     Reset value:
     MODER: 0x0000A000

INT_SOURCE
----------

Bit   Access   Description
31-7     Reserved
4   RW   BUSY   Busy
 This bit indicates that a buffer was received and discarded due to a lack of buffers. It is cleared by writing 1 to it. This bit appears regardless to the IRQ bits in the Receive or Transmit Buffer Descriptors.
3   RW   RXE   Receive error
 This bit indicates that an error occurred while receiving data. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Receive Buffer Descriptor.
2   RW   RXB   Receive buffer
 This bit indicates that a frame was received. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Receive Buffer Descriptor. If a control frame is received, then RXC bit is set instead of the RXB bit.
1   RW   TXE   Transmit error
 This bit indicates that a buffer was not transmitted due to a transmit error. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Receive Buffer Descriptor. This bit appears only when IRQ bit is set in the Transmit Buffer Descriptor.
0   RW   TXB   Transmit buffer
 This bit indicates that a buffer has been transmitted. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Transmit Buffer Descriptor.

     Reset value:
     INT_SOURCE: 0x00000000

INT_MASK
--------

Bit   Access   Description
31-7     Reserved
4   RW   BUSY_M   Busy mask

3   RW   RXE_M   Receive error
 Receive error mask
2   RW   RXB_M   Receive buffer
 Receive buffer mask
1   RW   TXE_M   Transmit error
 Transmit error mask
0   RW   TXB_M   Transmit buffer
 Transmit buffer mask

     Reset value:
     INT_MASK: 0x00000000

     0 -> event masked
     1 -> event causes an interrupt

TX_BD_NUM
---------

Bit   Access   Description
31-8     Reserved
7-0   RW   TX_BD_NUM   Transmit Buffer Descriptor Number
 Number of the Tx BD. Number of the Rx BD equals to the (0x80 – Tx BD number). Maximum number of the Tx BD is 0x80. Values greater then 0x80 cannot be written to this register (ignored).

     Reset value:
     TX_BD_NUM: 0x00000040

MIIMODER
--------

Bit   Access   Description
31-9     Reserved
8   RW   MIINOPRE   No Preamble
 0 = 32 bit preamble sent
 1 = No preamble sent
7-0   RW   CLKDIV   Clock divider The field is a host clock divider factor. The host clock can be divided by an even number, greater then 1. The default value is 0x64 (100).

     Reset value:
     MIIMODER: 0x00000064

MIICOMMAND
----------

Bit   Access   Description
31-3     Reserved
2   RW   WCTRLDATA   Write control data
1   RW   RSTAT   Read status
0   RW   SCANSTAT   Scan status

     Reset value:
     MIICOMMAND: 0x00000000

MIIADDRESS
----------

Bit   Access   Description
31-13     Reserved
12-8   RW   RGAD   Register address
7-5   RW   Reserved
4-0   RW   FIAD   PHY address

     Reset value:
     MIIADDRESS: 0x00000000

MIITX_DATA
----------

Bit   Access   Description
31-16     Reserved
15-0   RW   CTRLDATA   Data to be written to the PHY

     Reset value:
     MIITX_DATA: 0x00000000

MIIRX_DATA
----------

Bit   Access   Description
31-16     Reserved
15-0   R   PRSD   Data read from the PHY

     Reset value:
     MIIRX_DATA: 0x00000000

MIISTATUS
---------

Bit   Access   Description
31-3     Reserved
2   R   NVALID   Invalid
 0 = The data in the MSTATUS register is valid.
 1 = The data in the MSTATUS register is invalid.
 This bit is only valid when the scan status operation is active.
1   R   BUSY   0 = The MII is ready.
 1 = The MII is busy (operation in progress).
0   R   LINKFAIL   0 = The link is OK.
1 = The link failed.
The Link fail condition occurred (now the link might be OK). Another status read gets a new status.

     Reset value:
     MIISTATUS: 0x00000000

MAC_ADDR0
---------

Bit   Access   Description
31-24   RW   Byte 2 of the Ethernet MAC address
23-16   RW   Byte 3 of the Ethernet MAC address
15-8   RW   Byte 4 of the Ethernet MAC address
7-0   RW   Byte 5 of the Ethernet MAC address

     Reset value:
     MAC_ADDR0: 0x00000000

MAC_ADDR1
---------

Bit   Access   Description
31-16     Reserved
15-8   RW   Byte 0 of the Ethernet MAC address
7-0   RW   Byte 1 of the Ethernet MAC address

     Reset value:
     MAC_ADDR1: 0x00000000

Management Data Input/Output
****************************

The MDIO interface is implemented by two lines:

  * a MDC clock line

  * an MDIO data line

The clock line is driven by the MAC device. The data line is bidirectional: the PHY drives it to provide register data at the end of a read operation. The bus has a single MAC master, but can have up to 32 PHY slaves. The MDC clock can be aperiodic, with a minimum period of 400 ns, which corresponds to a maximal frequency of 2.5 MHz. Newer chips, however, allow faster acesses. The MDIO data line has a pull-up of 1.5 kOhm in the PHY, allowing the MAC to determine if one or more PHYs are attached. The MAC should have a 2 kOhm pull-down on that same line.

Bus timing
==========

Read operation
--------------

A read operation has the following phases

  * Preamble with 32 ones

  * Start sequence, 01

  * Opcode read, 10

  * PHY adress

  * REG adress

  * Bus turnaround

  * Register data

Write operation
---------------

A write operation has the following phases

  * Preamble with 32 ones

  * Start sequence, 01

  * Opcode read, 01

  * PHY adress

  * REG adress

  * Bus turnaround

  * Register data

Ingress and Egress FIFO
***********************

FIFO implementation
===================

Both ingress and egress FIFO implementation uses a generic asynchronous FIFO design available from OpenCores.

versatile_library (http://opencores.org/project)

GNU Free Documentation License
******************************

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