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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [tags/] [start/] [sim/] [rtl_sim/] [run/] [ncwork/] [hdl.var] - Rev 7
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#*****************************************************************************
# NCSIM hdl.var template *
#*****************************************************************************
#This file allows commonly used tool setups to be invoked automatically.
#All the switches may be alternatively specifed on the command line.
#reference the tool installation hdl.var - DO NOT REMOVE
INCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var
# These are default settings for NCVLOG, NCVHDL, NCELAB, NCSIM
# See below for commonly used switches.
DEFINE NCVLOGOPTS -NOCOPYRIGHT -UPDATE
DEFINE NCVHDLOPTS -NOCOPYRIGHT -UPDATE
DEFINE NCELABOPTS -NOCOPYRIGHT
DEFINE NCSIMOPTS -NOCOPYRIGHT -NOKEY -STATUS
#Maps the work library to a logical library.
#This library will contain the compiled design units
#Can be overriden on the command line with -work <library>
#DEFINE WORK work
DEFINE work ../ncwork
# Define valid Verilog file extensions
DEFINE VERILOG_SUFFIX (.v, .vr, .vb, .vg)
# Define valid VHDL file extensions
DEFINE VHDL_SUFFIX (.vhd, .vhdl)