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BRK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NOP 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
RTS 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
SIF 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Semaphore Instructions
CSEM IMM3 0 0 0 0 0 IMM3 1 1 1 1 0 0 0 0
CSEM RS 0 0 0 0 0 RS 1 1 1 1 0 0 0 1
SSEM IMM3 0 0 0 0 0 IMM3 1 1 1 1 0 0 1 0
SSEM RS 0 0 0 0 0 RS 1 1 1 1 0 0 1 1
Single Register Instructions
SEX RD 0 0 0 0 0 RD 1 1 1 1 0 1 0 0
PAR RD 0 0 0 0 0 RD 1 1 1 1 0 1 0 1
JAL RD 0 0 0 0 0 RD 1 1 1 1 0 1 1 0
SIF RS 0 0 0 0 0 RS 1 1 1 1 0 1 1 1
Special Move instructions
TFR RD,CCR 0 0 0 0 0 RD 1 1 1 1 1 0 0 0
TFR CCR,RS 0 0 0 0 0 RS 1 1 1 1 1 0 0 1
TFR RD,PC 0 0 0 0 0 RD 1 1 1 1 1 0 1 0
Shift instructions Dyadic
BFFO RD, RS 0 0 0 0 1 RD RS 1 0 0 0 0
ASR RD, RS 0 0 0 0 1 RD RS 1 0 0 0 1
CSL RD, RS 0 0 0 0 1 RD RS 1 0 0 1 0
CSR RD, RS 0 0 0 0 1 RD RS 1 0 0 1 1
LSL RD, RS 0 0 0 0 1 RD RS 1 0 1 0 0
LSR RD, RS 0 0 0 0 1 RD RS 1 0 1 0 1
ROL RD, RS 0 0 0 0 1 RD RS 1 0 1 1 0
ROR RD, RS 0 0 0 0 1 RD RS 1 0 1 1 1
Shift instructions immediate
ASR RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 0 1
CSL RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 1 0
CSR RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 1 1
LSL RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 0 0
LSR RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 0 1
ROL RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 1 0
ROR RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 1 1
Logical Triadic
AND RD, RS1, RS2 0 0 0 1 0 RD RS1 RS2 0 0
OR RD, RS1, RS2 0 0 0 1 0 RD RS1 RS2 1 0
XNOR RD, RS1, RS2 0 0 0 1 0 RD RS1 RS2 1 1
Arithmetic Triadic For compare use SUB R0,Rs1,Rs2
SUB RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 0 0
SBC RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 0 1
ADD RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 1 0
ADC RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 1 1
Branches
BCC REL9 0 0 1 0 0 0 0 REL9
BCS REL9 0 0 1 0 0 0 1 REL9
BNE REL9 0 0 1 0 0 1 0 REL9
BEQ REL9 0 0 1 0 0 1 1 REL9
BPL REL9 0 0 1 0 1 0 0 REL9
BMI REL9 0 0 1 0 1 0 1 REL9
BVC REL9 0 0 1 0 1 1 0 REL9
BVS REL9 0 0 1 0 1 1 1 REL9
BHI REL9 0 0 1 1 0 0 0 REL9
BLS REL9 0 0 1 1 0 0 1 REL9
BGE REL9 0 0 1 1 0 1 0 REL9
BLT REL9 0 0 1 1 0 1 1 REL9
BGT REL9 0 0 1 1 1 0 0 REL9
BLE REL9 0 0 1 1 1 0 1 REL9
BRA REL10 0 0 1 1 1 1 REL10
Load and Store Instructions
LDB RD, (RB, #OFFS5) 0 1 0 0 0 RD RB OFFS5
LDW RD, (RB, #OFFS5) 0 1 0 0 1 RD RB OFFS5
STB RS, (RB, #OFFS5) 0 1 0 1 0 RS RB OFFS5
STW RS, (RB, #OFFS5) 0 1 0 1 1 RS RB OFFS5
LDB RD, (RB, RI) 0 1 1 0 0 RD RB RI 0 0
LDW RD, (RB, RI) 0 1 1 0 1 RD RB RI 0 0
STB RS, (RB, RI) 0 1 1 1 0 RS RB RI 0 0
STW RS, (RB, RI) 0 1 1 1 1 RS RB RI 0 0
LDB RD, (RB, RI+) 0 1 1 0 0 RD RB RI 0 1
LDW RD, (RB, RI+) 0 1 1 0 1 RD RB RI 0 1
STB RS, (RB, RI+) 0 1 1 1 0 RS RB RI 0 1
STW RS, (RB, RI+) 0 1 1 1 1 RS RB RI 0 1
LDB RD, (RB, –RI) 0 1 1 0 0 RD RB RI 1 0
LDW RD, (RB, –RI) 0 1 1 0 1 RD RB RI 1 0
STB RS, (RB, –RI) 0 1 1 1 0 RS RB RI 1 0
STW RS, (RB, –RI) 0 1 1 1 1 RS RB RI 1 0
Bit Field Instructions
BFEXT RD, RS1, RS2 0 1 1 0 0 RD RS1 RS2 1 1
BFINS RD, RS1, RS2 0 1 1 0 1 RD RS1 RS2 1 1
BFINSI RD, RS1, RS2 0 1 1 1 0 RD RS1 RS2 1 1
BFINSX RD, RS1, RS2 0 1 1 1 1 RD RS1 RS2 1 1
Logic Immediate Instructions
ANDL RD, #IMM8 1 0 0 0 0 RD IMM8
ANDH RD, #IMM8 1 0 0 0 1 RD IMM8
BITL RD, #IMM8 1 0 0 1 0 RD IMM8
BITH RD, #IMM8 1 0 0 1 1 RD IMM8
ORL RD, #IMM8 1 0 1 0 0 RD IMM8
ORH RD, #IMM8 1 0 1 0 1 RD IMM8
XNORL RD, #IMM8 1 0 1 1 0 RD IMM8
XNORH RD, #IMM8 1 0 1 1 1 RD IMM8
Arithmetic Immediate Instructions
SUBL RD, #IMM8 1 1 0 0 0 RD IMM8
SUBH RD, #IMM8 1 1 0 0 1 RD IMM8
CMPL RS, #IMM8 1 1 0 1 0 RS IMM8
CPCH RS, #IMM8 1 1 0 1 1 RS IMM8
ADDL RD, #IMM8 1 1 1 0 0 RD IMM8
ADDH RD, #IMM8 1 1 1 0 1 RD IMM8
LDL RD, #IMM8 1 1 1 1 0 RD IMM8
LDH RD, #IMM8 1 1 1 1 1 RD IMM8