Zorro to Wishbone Bridge
Specification

Author: [William Toner]

[amigabill@gmail.com]

Rev. [0.1]

May 12, 2011

Licensed under Gnu LGPL 2 or higher

This page has been intentionally left blank.

Revision History

Rev.	Date	Author	Description
0.1	XX/XX/XX	William Toner	First Draft [Example – delete and print your own comments]
0.2	XX/XX/XX	[NAME]	Removed Header and Footer on Title Page. Changed Page numbering to start after Title Page. Changed Document Title Font to Times. [Example – delete and print your own comments]
0.3	XX/XX/XX	[NAME]	Changed OpenCores.com to OpenCores.org. Changed tables so WISHBONE signals fit into cells, centered width column. Changed page-numbering, start counting from Introduction page using Arabic numbers. Use Roman numbers for other pages. Changed date on title page to autoupdate. Added Contents page, used crosslinks for automatic header and page number generation. [Example – delete and print your own comments]

Contents

Introduction	1

Architecture	2

Operation	3

Registers	4

List of Registers	4

Register 1 – Description	4

Clocks	5

IO Ports	6

Introduction

This IP Core intends to operate as a bridge between the Wishbone bus defined by Opencores.org and the Amiga Zorro bus defined by Commodore-Amiga.

Wishbone is the System on Chip (SoC) bus standard promoted by Opencores.org, and is used by many free/open-source peripherals available there. Current version is B.4, though a number of IP cores on the website likely use version B.3, as B.4 is a recent update as of this writing.

Zorro II and Zorro III are bus standards from Commodore Amiga, as used in their Amiga 2000, 3000 and 4000 series computers from 1985 and later. Zorro II is a 16bit data bus with 24bit addressing, and is essentially the Motorola 68000 CPU bus with a few enhancements. Zorro III is a 32bit data and address bus running asynchronously, yet provides for backward Zorro II compatibility, such that any Zorro II peripheral designed to supported Commodore spec is expected to work properly in a Zorro III host. Also, a number of ZorroIII addon cards were designed such that they could also work when plugged into a ZorroII slot. Both ZorroII and ZorroIII feature Autoconfig capability, where the operating system scans for and configured all expansion cards in the system. Later, PCI came along with similar automatic configuration capability. ZorroII and ZorroIII peripherals can be slave-only devices, or they can be busmaster devices which can control the bus themselves, and can run DMA accesses if supported by the design and driver software.

Note that the ZorroII and ZorroIII specs are defined as a PCB bus, including bidis, tristates, open-collector outputs, etc. Convert such things to dual bus (one for inout, one for output, and output-enable where necessary for tristate/open-collector type PCB signals.), muxed busses, output-enables, etc. as needed for internal chip logic consideration.

Since an FPGA can easily be attached to the Amiga Zorro II or Zorro III bus, softcore peripherals can easily be incorporated into the Zorro host system. There are a number of free and open-source peripheral softcores available to attach to a Wishbone bus, many at www.opencores.org . Thus, a bridge between Zorro and Wishbone can provide for a number of peripherals in an Amiga or other system using the ZorroII or ZorroIII bus, as well as for adding a Zorro bus to a Wishbone based system. A final usage of this IP could replace the Buster or Super Buster chip in an Amiga computer, with the intent of correcting bugs in the Commodore design, as well as to increase bus troughput compared to the older Commodore design.

Commodore defined system memory map locations for ZorroII and ZorroIII address space, which were honored by the “Kickstart” firmware and the Amiga Operating System software. As the locations of things kept things standardized for the Amiga computer systems, it was important to maintain those address locations for compatibility. For designers of other systems, who will create their own firmware and operating system code, it may be tempting to redefine address locations, and in cases of complete new design without using any legacy Zorro peripheral cards from Amiga history, this may be fine. But keep in mind that Zorro peripheral cards look for certain addresses at Autoconfig time, and may have assigned address limitations related to Commodore's memory map definitions.

Minimig is an open-source reimplementation of the Commodore Amiga computer design, and this Zorro to Wishbone bridge may be most appealing to experimenters and retro fan users of Minimig computers, but it may also be interesting for people desiring an automatically configuring bus architecture for other platforms as well, as Autoconfig could assist with peripheral configuration in a modular System on Chip (SoC) design. Minimig is essentially an Amiga SoC platform, though has to date been limited to features and peripherals similar to the simple Amiga 500 model computer from the 1980's, and has so far lacked an external expansion bus of any kind.

This bridge project intends to offer the design in Verilog RTL, as well as offer Verilog testbench for simulation. Ideally, Minimig could allow full system simulations including software compilation and simulation runtime testing, but I am not sure at the moment what limitations free and open-source simulators will have that make such a thing difficult or unbearable.

Wishbone Classic master simple read from ZorroII slave

Wishbone Classic master BLOCK read from ZorroII slave

Wishbone Classic master BLOCK pipeline read from ZorroII slave

Wishbone Classic master simple write to ZorroII slave

Wishbone Classic master BLOCK write to ZorroII slave

Wishbone Classic master BLOCK pipeline write to ZorroII slave

ZorroII master simple read from Wishbone Classic slave

ZorroII master BLOCK read from Wishbone Classic slave

Zorro II master BLOCK pipeline read from Wishbone Classic slave

ZorroII master simple write to Wishbone Classic slave

ZorroII master BLOCK write to Wishbone Classic slave

ZorroII master BLOCK pipeline write to Wishbone Classic slave

DMA from ZorroII to Wishbone

DMA from Wishbone to ZorroII

Wishbone Classic master read from ZorroIII slave

Wishbone Classic master BLOCK read from ZoroIII slave

Wishbone Classic master BLOCK pipeline read from ZorroIII slave

Wishbone Classic master write to ZorroIII slave

ZorroIII master read from Wishbone slave

ZorroIII master write to Wishbone slave

DMA from ZorroIII to Wishbone

DMA from Wishbone to ZorroIII

Interrupts

Wishbone peripheral interrupting Zorro II host

Wishbone peripheral interrupting Zorro III host

ZorroII peripheral interrupting Wishbone host

Zorro III peripheral interrupting Wishbone host

Bus arbitration for Zorro host system controller configuration

Architecture

[This section describes the architecture of the block. A block diagram should be included describing the top level of the design.]

Operation

[This section describes the operation of the core. Specific sequences, such as startup sequences, as well as the modes and states of the block should be described.]

For those wishing to use this bridge to connect Wishbone peripherals to a Zorro host, you will need to aquire an Autoconfig Manufacturer ID from Olaf Barthel, if you do not already have one. [Need to determine acceptable conact method to mention here]

For those wishing to use this bridge to connect Zorro peripherals to a Wishbone host, you will not need an Autoconfig Manufacturer ID.

Registers

[This section specifies all internal registers. It should completely cover the interface between the core and the host as seen from the software view.]

List of Registers

Name	Address	Width	Access	Description

Table 1: List of registers

Register 1 – Description

[You shall choose the style of register you prefer. Do not use both options in one and the same document.]

Bit #	Access	Description

Reset Value:

Reg_Name: 0000h

31	30	29	28	...	8	7	6	5	4	3	2	1	0

Table 2: Description of registers

Reset Value:

Reg_Name: 0000h

Clocks

[This section specifies all the clocks. All clocks, clock domain passes and the clock relations should be described.]

Name	Source	Rates (MHz)	Remarks	Description
Max	Min	Resolution
wb_clk_I	Wishbone bus clock
z23_7m_clk_in	7MHz main Zorro bus clock. Equivalent to MC68000 7M clock.
z23_cdac_clk_in
z23_Nc1_clk_in
z23_Nc3_clk_in
z23_e_clk_in
sm_clock_in	System clock driving the state machine

Table 3: List of clocks

IO Ports

[This section specifies the core IO ports.]

Port	Width	Direction	Description
wb_clk_i	1	Input	Block’s WISHBONE Clock Input
wb_rst_i	1	Input	Block’s WISHBONE Reset Input
wb_sel_i	4	Input	Block’s WISHBONE Select Inputs
foo_pad_o	1	Output	Block’s foo output to output pad
…

Table 4: List of IO ports

Appendix A

Zorro PCB level pinouts

Appendix B

Buster information for Amiga 2000 series computers

This information is provided in the event someone desires to use this bridge as part of a project to replace the Commodore Amiga design Buster chip used in Amiga 2000 family computers.

Amiga 2000 Memory Map

Appendix C

Super Buster information for Amiga 3000 and 4000 series computers

This information is provided in the event someone desires to use this bridge as part of a project to replace the Commodore Amiga design Super Buster chip used in Amiga 3000 and 4000 family computers.

Amiga 3000/4000 Memory Map

[This section contains an alphabetical list of helpful document entries with their corresponding page numbers.]