#### Generation Settings

Component declarations | yes
Configurations | embedded statements
add pragmas
exclude view name

#### Declarations

#### Ports:

    clk_clk_i       : std_logic
    rst_rst_n_i     : std_logic
    sel_pc_in_i     : std_logic
    ld_i            : std_logic_vector(1 DOWNTO 0)
    adr_i           : std_logic_vector(15 DOWNTO 0)
    adr_pc_o        : std_logic_vector(15 DOWNTO 0)
    sel_pc_val_i    : std_logic_vector(1 DOWNTO 0)
    offset_i        : std_logic_vector(15 DOWNTO 0)
    ld_pc_i         : std_logic
    adr_nxt_pc_o    : std_logic_vector(15 DOWNTO 0)

#### Diagram Signals:

    signal load_o_i        : std_logic
    signal val_zero        : std_logic_vector(7 DOWNTO 0)
    signal val_one         : std_logic_vector(7 DOWNTO 0)
    signal cout_pc_o_i     : std_logic
    signal load3_o_i       : std_logic
    signal val_o_i         : std_logic_vector(7 DOWNTO 0)
    signal ci_o_i          : std_logic
    signal adr_pc_o_i      : std_logic_vector(15 DOWNTO 0)
    signal adr_pc_low_o_i  : std_logic_vector(7 DOWNTO 0)
    signal adr_pc_high_o_i : std_logic_vector(7 DOWNTO 0)
    signal offset_low_o_i  : std_logic_vector(7 DOWNTO 0)
    signal offset_high_o_i : std_logic_vector(7 DOWNTO 0)

#### Pre User:

#### Post User:

#### Package List

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;

#### Bundles