#### Generation Settings

Component declarations | yes
Configurations | embedded statements
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#### Declarations

#### Ports:

    clk_clk_i   : std_logic
    d_i         : std_logic_vector(7 DOWNTO 0)
    so_n_i      : std_logic
    rdy_i       : std_logic
    irq_n_i     : std_logic
    nmi_n_i     : std_logic
    rst_rst_n_i : std_logic
    a_o         : std_logic_vector(15 DOWNTO 0)
    d_o         : std_logic_vector(7 DOWNTO 0)
    rd_o        : std_logic
    wr_o        : std_logic
    wr_n_o      : std_logic
    sync_o      : std_logic

#### Diagram Signals:

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#### Package List

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;

#### Bundles