#### Signal Status

NAME | MODE | SCHEME | DEFAULT | RESET
a_o | out | Comb | sig_PC |
adr_o | out | Comb | X"0000" |
ch_a_o | out | Comb | X"00" |
ch_b_o | out | Comb | X"00" |
d_o | out | Clocked | sig_D_OUT | X"00"
d_regs_in_o | out | Comb | X"00" |
int_fetch_o | out | Comb | '0' |
int_reg_2flag_o | out | Comb | reg_F(2) |
ld_o | out | Comb | "00" |
ld_pc_o | out | Comb | '0' |
ld_sp_o | out | Comb | '0' |
load_regs_o | out | Comb | '0' |
offset_o | out | Comb | X"0000" |
rd_o | out | Clocked | sig_RD | '0'
rst_nmi_o | out | Comb | '0' |
sel_pc_in_o | out | Comb | reg_sel_pc_in |
sel_pc_val_o | out | Comb | reg_sel_pc_val |
sel_rb_in_o | out | Comb | reg_sel_rb_in |
sel_rb_out_o | out | Comb | reg_sel_rb_out |
sel_reg_o | out | Comb | reg_sel_reg |
sel_sp_as_o | out | Comb | reg_sel_sp_as |
sel_sp_in_o | out | Comb | reg_sel_sp_in |
sync_o | out | Clocked | sig_SYNC | '0'
wr_n_o | out | Clocked | sig_RWn | '1'
wr_o | out | Clocked | sig_WR | '0'
reg_F | LOCAL | Clocked | reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0) | "00110100"
reg_sel_pc_in | LOCAL | Clocked | reg_sel_pc_in | '0'
reg_sel_pc_val | LOCAL | Clocked | reg_sel_pc_val | "00"
reg_sel_rb_in | LOCAL | Clocked | reg_sel_rb_in | "00"
reg_sel_rb_out | LOCAL | Clocked | reg_sel_rb_out | "00"
reg_sel_reg | LOCAL | Clocked | reg_sel_reg | "00"
reg_sel_sp_as | LOCAL | Clocked | reg_sel_sp_as | '0'
reg_sel_sp_in | LOCAL | Clocked | reg_sel_sp_in | '0'
sig_D_OUT | LOCAL | Comb | X"00" |
sig_PC | LOCAL | Clocked | sig_PC | X"0000"
sig_RD | LOCAL | Comb | '1' |
sig_RWn | LOCAL | Comb | '1' |
sig_SYNC | LOCAL | Comb | '0' |
sig_WR | LOCAL | Comb | '0' |
zw_REG_OP | LOCAL | Clocked | zw_REG_OP | X"00"
zw_alu | LOCAL | Comb | "00" & X"00" |
zw_alu1 | LOCAL | Comb | "00" & X"00" |
zw_alu2 | LOCAL | Comb | "00" & X"00" |
zw_alu3 | LOCAL | Comb | "00" & X"00" |
zw_alu4 | LOCAL | Comb | "00" & X"00" |
zw_b1 | LOCAL | Clocked | zw_b1 | X"00"
zw_b2 | LOCAL | Clocked | zw_b2 | X"00"
zw_b3 | LOCAL | Clocked | zw_b3 | X"00"
zw_b4 | LOCAL | Clocked | zw_b4 | X"00"
zw_bit | LOCAL | Clocked | zw_bit | '0'
zw_irq | LOCAL | Clocked | zw_irq | '0'
zw_ninebits4 | LOCAL | Comb | '0' & X"00" |
zw_nmi | LOCAL | Clocked | zw_nmi | '0'
zw_so | LOCAL | Clocked | (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6))) | '0'

#### Generation Settings

Machine | "csm", synchronous
Encoding | hard : gray
Style | case, 2 processes
Clock | "clk_clk_i", rising
Reset | "rst_rst_n_i", asynchronous, active low
State variable type | [auto]
Default state assignment disabled
State actions registered on current state

#### Architecture Declarations

#### Global Actions

#### Pre Actions:

#### Post Actions:

#### Concurrent Statements

#### State Register Statements

#### VHDL Process Declarations

#### Clocked Process:

#### Output Process:

#### Package List

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;