#### Generation Settings

Component declarations | yes
Configurations | embedded statements
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#### Declarations

#### Ports:

    clk_clk_i    : std_logic
    rst_rst_n_i  : std_logic
    d_regs_in_i  : std_logic_vector(7 DOWNTO 0)
    sel_rb_in_i  : std_logic_vector(1 DOWNTO 0)
    sel_rb_out_i : std_logic_vector(1 DOWNTO 0)
    load_regs_i  : std_logic
    q_a_o        : std_logic_vector(7 DOWNTO 0)
    q_x_o        : std_logic_vector(7 DOWNTO 0)
    q_y_o        : std_logic_vector(7 DOWNTO 0)
    d_regs_out_o : std_logic_vector(7 DOWNTO 0)
    sel_reg_i    : std_logic_vector(1 DOWNTO 0)

#### Diagram Signals:

    signal ld           : std_logic_vector(2 DOWNTO 0)
    signal load_o_i     : std_logic
    signal load1_o_i    : std_logic
    signal load2_o_i    : std_logic
    signal q_mux_o_i    : std_logic_vector(7 DOWNTO 0)
    signal val_zero     : std_logic_vector(7 DOWNTO 0)

#### Pre User:

#### Post User:

#### Package List

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;

#### Bundles