#### Signal Status

NAME | MODE | SCHEME | DEFAULT | RESET
nmi_o | out | Clocked | '0' | '0'

#### Generation Settings

Machine | "csm", synchronous
Encoding | hard : gray
Style | case, 3 processes
Clock | "clk_clk_i", rising
Reset | "rst_rst_n_i", asynchronous, active low
State variable type | [auto]
Default state assignment disabled
State actions registered on current state

#### Architecture Declarations

#### Global Actions

#### Pre Actions:

#### Post Actions:

#### Concurrent Statements

#### State Register Statements

#### VHDL Process Declarations

#### Clocked Process:

#### Output Process:

#### Package List

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;