#### Generation Settings

Component declarations | yes
Configurations | embedded statements
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#### Declarations

#### Ports:

    clk_clk_i       : std_logic
    rst_rst_n_i     : std_logic
    sel_sp_in_i     : std_logic
    ld_low_i        : std_logic
    adr_low_i       : std_logic_vector(7 DOWNTO 0)
    adr_sp_o        : std_logic_vector(15 DOWNTO 0)
    sel_sp_as_i     : std_logic
    ld_sp_i         : std_logic

#### Diagram Signals:

    signal val_one         : std_logic_vector(7 DOWNTO 0)
    signal sp_as_n_o_i     : std_logic
    signal load_o_i        : std_logic
    signal adr_sp_low_o_i  : std_logic_vector(7 DOWNTO 0)
    signal result_low_o_i  : std_logic_vector(7 DOWNTO 0)
    signal result_low1_o_i : std_logic_vector(7 DOWNTO 0)

#### Pre User:

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#### Package List

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;

#### Bundles