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<H1><A NAME="section_1">15 LISTING OF data_mem.vhd</A></H1>
 
<pre class="vhdl">
 
  1	-------------------------------------------------------------------------------
  2	-- 
  3	-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
  4	-- 
  5	--  This code is free software: you can redistribute it and/or modify
  6	--  it under the terms of the GNU General Public License as published by
  7	--  the Free Software Foundation, either version 3 of the License, or
  8	--  (at your option) any later version.
  9	--
 10	--  This code is distributed in the hope that it will be useful,
 11	--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 12	--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13	--  GNU General Public License for more details.
 14	--
 15	--  You should have received a copy of the GNU General Public License
 16	--  along with this code (see the file named COPYING).
 17	--  If not, see http://www.gnu.org/licenses/.
 18	--
 19	-------------------------------------------------------------------------------
 20	-------------------------------------------------------------------------------
 21	--
 22	-- Module Name:    data_mem - Behavioral 
 23	-- Create Date:    14:09:04 10/30/2009 
 24	-- Description:    the data mempry of a CPU.
 25	--
 26	-------------------------------------------------------------------------------
 27	--
 28	library IEEE;
 29	use IEEE.STD_LOGIC_1164.ALL;
 30	use IEEE.STD_LOGIC_ARITH.ALL;
 31	use IEEE.STD_LOGIC_UNSIGNED.ALL;
 32	
 33	---- Uncomment the following library declaration if instantiating
 34	---- any Xilinx primitives in this code.
 35	-- library UNISIM;
 36	-- use UNISIM.VComponents.all;
 37	
 38	entity data_mem is
 39	    port (  I_CLK       : in  std_logic;
 40	
 41	            I_ADR       : in  std_logic_vector(10 downto 0);
 42	            I_DIN       : in  std_logic_vector(15 downto 0);
 43	            I_WE        : in  std_logic_vector( 1 downto 0);
 44	
 45	            Q_DOUT      : out std_logic_vector(15 downto 0));
 46	end data_mem;
 47	
 48	architecture Behavioral of data_mem is
 49	 
 50	constant zero_256 : bit_vector := X"00000000000000000000000000000000"
 51	                                & X"00000000000000000000000000000000";
 52	constant nine_256 : bit_vector := X"99999999999999999999999999999999"
 53	                                & X"99999999999999999999999999999999";
 54	
 55	component RAMB4_S4_S4
 56	    generic(INIT_00 : bit_vector := zero_256;
 57	            INIT_01 : bit_vector := zero_256;
 58	            INIT_02 : bit_vector := zero_256;
 59	            INIT_03 : bit_vector := zero_256;
 60	            INIT_04 : bit_vector := zero_256;
 61	            INIT_05 : bit_vector := zero_256;
 62	            INIT_06 : bit_vector := zero_256;
 63	            INIT_07 : bit_vector := zero_256;
 64	            INIT_08 : bit_vector := zero_256;
 65	            INIT_09 : bit_vector := zero_256;
 66	            INIT_0A : bit_vector := zero_256;
 67	            INIT_0B : bit_vector := zero_256;
 68	            INIT_0C : bit_vector := zero_256;
 69	            INIT_0D : bit_vector := zero_256;
 70	            INIT_0E : bit_vector := zero_256;
 71	            INIT_0F : bit_vector := zero_256);
 72	
 73	    port(   DOA     : out std_logic_vector(3 downto 0);
 74	            DOB     : out std_logic_vector(3 downto 0);
 75	            ADDRA   : in  std_logic_vector(9 downto 0);
 76	            ADDRB   : in  std_logic_vector(9 downto 0);
 77	            CLKA    : in  std_ulogic;
 78	            CLKB    : in  std_ulogic;
 79	            DIA     : in  std_logic_vector(3 downto 0);
 80	            DIB     : in  std_logic_vector(3 downto 0);
 81	            ENA     : in  std_ulogic;
 82	            ENB     : in  std_ulogic;
 83	            RSTA    : in  std_ulogic;
 84	            RSTB    : in  std_ulogic;
 85	            WEA     : in  std_ulogic;
 86	            WEB     : in  std_ulogic);
 87	end component;
 88	
 89	signal L_ADR_0      : std_logic;
 90	signal L_ADR_E      : std_logic_vector(10 downto 1);
 91	signal L_ADR_O      : std_logic_vector(10 downto 1);
 92	signal L_DIN_E      : std_logic_vector( 7 downto 0);
 93	signal L_DIN_O      : std_logic_vector( 7 downto 0);
 94	signal L_DOUT_E     : std_logic_vector( 7 downto 0);
 95	signal L_DOUT_O     : std_logic_vector( 7 downto 0);
 96	signal L_WE_E       : std_logic;
 97	signal L_WE_O       : std_logic;
 98	 
 99	begin
100	
101	    sr_0 : RAMB4_S4_S4 ---------------------------------------------------------
102	    generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
103	                INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
104	                INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
105	                INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
106	                INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
107	                INIT_0F => nine_256)
108	
109	    port map(   ADDRA => L_ADR_E,               ADDRB => "0000000000",
110	                CLKA  => I_CLK,                 CLKB  => I_CLK,
111	                DIA   => L_DIN_E(3 downto 0),   DIB   => "0000",
112	                ENA   => '1',                   ENB   => '0',
113	                RSTA  => '0',                   RSTB  => '0',
114	                WEA   => L_WE_E,                WEB   => '0',
115	                DOA   => L_DOUT_E(3 downto 0),  DOB   => open);
116	 
117	    sr_1 : RAMB4_S4_S4 ---------------------------------------------------------
118	    generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
119	                INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
120	                INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
121	                INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
122	                INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
123	                INIT_0F => nine_256)
124	
125	    port map(   ADDRA => L_ADR_E,               ADDRB => "0000000000",
126	                CLKA  => I_CLK,                 CLKB  => I_CLK,
127	                DIA   => L_DIN_E(7 downto 4),   DIB   => "0000",
128	                ENA   => '1',                   ENB   => '0',
129	                RSTA  => '0',                   RSTB  => '0',
130	                WEA   => L_WE_E,                WEB   => '0',
131	                DOA   => L_DOUT_E(7 downto 4),  DOB   => open);
132	 
133	    sr_2 : RAMB4_S4_S4 ---------------------------------------------------------
134	    generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
135	                INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
136	                INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
137	                INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
138	                INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
139	                INIT_0F => nine_256)
140	
141	    port map(   ADDRA => L_ADR_O,               ADDRB => "0000000000",
142	                CLKA  => I_CLK,                 CLKB  => I_CLK,
143	                DIA   => L_DIN_O(3 downto 0),   DIB   => "0000",
144	                ENA   => '1',                   ENB   => '0',
145	                RSTA  => '0',                   RSTB  => '0',
146	                WEA   => L_WE_O,                WEB   => '0',
147	                DOA   => L_DOUT_O(3 downto 0),  DOB   => open);
148	 
149	    sr_3 : RAMB4_S4_S4 ---------------------------------------------------------
150	    generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
151	                INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
152	                INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
153	                INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
154	                INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
155	                INIT_0F => nine_256)
156	
157	    port map(   ADDRA => L_ADR_O,               ADDRB => "0000000000",
158	                CLKA  => I_CLK,                 CLKB  => I_CLK,
159	                DIA   => L_DIN_O(7 downto  4),  DIB   => "0000",
160	                ENA   => '1',                   ENB   => '0',
161	                RSTA  => '0',                   RSTB  => '0',
162	                WEA   => L_WE_O,                WEB   => '0',
163	                DOA   => L_DOUT_O(7 downto  4), DOB   => open);
164	 
165	
166	    -- remember ADR(0)
167	    --
168	    adr0: process(I_CLK)
169	    begin
170	        if (rising_edge(I_CLK)) then
171	            L_ADR_0 <= I_ADR(0);
172	        end if;
173	    end process;
174	
175	    -- we use two memory blocks _E and _O (even and odd).
176	    -- This gives us a memory with ADR and ADR + 1 at th same time.
177	    -- The second port is currently unused, but may be used later,
178	    -- e.g. for DMA.
179	    --
180	
181	    L_ADR_O <= I_ADR(10 downto 1);
182	    L_ADR_E <= I_ADR(10 downto 1) + ("000000000" & I_ADR(0));
183	
184	    L_DIN_E <= I_DIN( 7 downto 0) when (I_ADR(0) = '0') else I_DIN(15 downto 8);
185	    L_DIN_O <= I_DIN( 7 downto 0) when (I_ADR(0) = '1') else I_DIN(15 downto 8);
186	
187	    L_WE_E <= I_WE(1) or (I_WE(0) and not I_ADR(0));
188	    L_WE_O <= I_WE(1) or (I_WE(0) and     I_ADR(0));
189	
190	    Q_DOUT( 7 downto 0) <= L_DOUT_E when (L_ADR_0 = '0') else L_DOUT_O;
191	    Q_DOUT(15 downto 8) <= L_DOUT_E when (L_ADR_0 = '1') else L_DOUT_O;
192	 
193	end Behavioral;
194	
<pre class="filename">
src/data_mem.vhd
</pre></pre>
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