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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <HTML> <HEAD> <TITLE>html/Listing_of_reg_16.vhd</TITLE> <META NAME="generator" CONTENT="HTML::TextToHTML v2.46"> <LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css"> </HEAD> <BODY> <P><table class="ttop"><th class="tpre"><a href="21_Listing_of_prog_mem.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="23_Listing_of_register_file.vhd.html">Next Lesson</a></th></table> <hr> <H1><A NAME="section_1">22 LISTING OF reg_16.vhd</A></H1> <pre class="vhdl"> 1 ------------------------------------------------------------------------------- 2 -- 3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann 4 -- 5 -- This code is free software: you can redistribute it and/or modify 6 -- it under the terms of the GNU General Public License as published by 7 -- the Free Software Foundation, either version 3 of the License, or 8 -- (at your option) any later version. 9 -- 10 -- This code is distributed in the hope that it will be useful, 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 -- GNU General Public License for more details. 14 -- 15 -- You should have received a copy of the GNU General Public License 16 -- along with this code (see the file named COPYING). 17 -- If not, see http://www.gnu.org/licenses/. 18 -- 19 ------------------------------------------------------------------------------- 20 ------------------------------------------------------------------------------- 21 -- 22 -- Module Name: Register - Behavioral 23 -- Create Date: 12:37:55 10/28/2009 24 -- Description: a register pair of a CPU. 25 -- 26 ---------------------------------------------------------------------------------- 27 library IEEE; 28 use IEEE.STD_LOGIC_1164.ALL; 29 use IEEE.STD_LOGIC_ARITH.ALL; 30 use IEEE.STD_LOGIC_UNSIGNED.ALL; 31 32 entity reg_16 is 33 port ( I_CLK : in std_logic; 34 35 I_D : in std_logic_vector (15 downto 0); 36 I_WE : in std_logic_vector ( 1 downto 0); 37 38 Q : out std_logic_vector (15 downto 0)); 39 end reg_16; 40 41 architecture Behavioral of reg_16 is 42 43 signal L : std_logic_vector (15 downto 0) := X"7777"; 44 begin 45 46 process(I_CLK) 47 begin 48 if (rising_edge(I_CLK)) then 49 if (I_WE(1) = '1') then 50 L(15 downto 8) <= I_D(15 downto 8); 51 end if; 52 if (I_WE(0) = '1') then 53 L( 7 downto 0) <= I_D( 7 downto 0); 54 end if; 55 end if; 56 end process; 57 58 Q <= L; 59 60 end Behavioral; 61 <pre class="filename"> src/reg_16.vhd </pre></pre> <P> <P><hr><BR> <table class="ttop"><th class="tpre"><a href="21_Listing_of_prog_mem.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="23_Listing_of_register_file.vhd.html">Next Lesson</a></th></table> </BODY> </HTML>