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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <HTML> <HEAD> <TITLE>html/Listing_of_register_file.vhd</TITLE> <META NAME="generator" CONTENT="HTML::TextToHTML v2.46"> <LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css"> </HEAD> <BODY> <P><table class="ttop"><th class="tpre"><a href="22_Listing_of_reg_16.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="24_Listing_of_segment7.vhd.html">Next Lesson</a></th></table> <hr> <H1><A NAME="section_1">23 LISTING OF register_file.vhd</A></H1> <pre class="vhdl"> 1 ------------------------------------------------------------------------------- 2 -- 3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann 4 -- 5 -- This code is free software: you can redistribute it and/or modify 6 -- it under the terms of the GNU General Public License as published by 7 -- the Free Software Foundation, either version 3 of the License, or 8 -- (at your option) any later version. 9 -- 10 -- This code is distributed in the hope that it will be useful, 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 -- GNU General Public License for more details. 14 -- 15 -- You should have received a copy of the GNU General Public License 16 -- along with this code (see the file named COPYING). 17 -- If not, see http://www.gnu.org/licenses/. 18 -- 19 ------------------------------------------------------------------------------- 20 ------------------------------------------------------------------------------- 21 -- 22 -- Module Name: RegisterFile - Behavioral 23 -- Create Date: 12:43:34 10/28/2009 24 -- Description: a register file (16 register pairs) of a CPU. 25 -- 26 ------------------------------------------------------------------------------- 27 -- 28 library IEEE; 29 use IEEE.STD_LOGIC_1164.ALL; 30 use IEEE.STD_LOGIC_ARITH.ALL; 31 use IEEE.STD_LOGIC_UNSIGNED.ALL; 32 33 use work.common.ALL; 34 35 entity register_file is 36 port ( I_CLK : in std_logic; 37 38 I_AMOD : in std_logic_vector( 5 downto 0); 39 I_COND : in std_logic_vector( 3 downto 0); 40 I_DDDDD : in std_logic_vector( 4 downto 0); 41 I_DIN : in std_logic_vector(15 downto 0); 42 I_FLAGS : in std_logic_vector( 7 downto 0); 43 I_IMM : in std_logic_vector(15 downto 0); 44 I_RRRR : in std_logic_vector( 4 downto 1); 45 I_WE_01 : in std_logic; 46 I_WE_D : in std_logic_vector( 1 downto 0); 47 I_WE_F : in std_logic; 48 I_WE_M : in std_logic; 49 I_WE_XYZS : in std_logic; 50 51 Q_ADR : out std_logic_vector(15 downto 0); 52 Q_CC : out std_logic; 53 Q_D : out std_logic_vector(15 downto 0); 54 Q_FLAGS : out std_logic_vector( 7 downto 0); 55 Q_R : out std_logic_vector(15 downto 0); 56 Q_S : out std_logic_vector( 7 downto 0); 57 Q_Z : out std_logic_vector(15 downto 0)); 58 end register_file; 59 60 architecture Behavioral of register_file is 61 62 component reg_16 63 port ( I_CLK : in std_logic; 64 65 I_D : in std_logic_vector(15 downto 0); 66 I_WE : in std_logic_vector( 1 downto 0); 67 68 Q : out std_logic_vector(15 downto 0)); 69 end component; 70 71 signal R_R00 : std_logic_vector(15 downto 0); 72 signal R_R02 : std_logic_vector(15 downto 0); 73 signal R_R04 : std_logic_vector(15 downto 0); 74 signal R_R06 : std_logic_vector(15 downto 0); 75 signal R_R08 : std_logic_vector(15 downto 0); 76 signal R_R10 : std_logic_vector(15 downto 0); 77 signal R_R12 : std_logic_vector(15 downto 0); 78 signal R_R14 : std_logic_vector(15 downto 0); 79 signal R_R16 : std_logic_vector(15 downto 0); 80 signal R_R18 : std_logic_vector(15 downto 0); 81 signal R_R20 : std_logic_vector(15 downto 0); 82 signal R_R22 : std_logic_vector(15 downto 0); 83 signal R_R24 : std_logic_vector(15 downto 0); 84 signal R_R26 : std_logic_vector(15 downto 0); 85 signal R_R28 : std_logic_vector(15 downto 0); 86 signal R_R30 : std_logic_vector(15 downto 0); 87 signal R_SP : std_logic_vector(15 downto 0); -- stack pointer 88 89 component status_reg is 90 port ( I_CLK : in std_logic; 91 92 I_COND : in std_logic_vector ( 3 downto 0); 93 I_DIN : in std_logic_vector ( 7 downto 0); 94 I_FLAGS : in std_logic_vector ( 7 downto 0); 95 I_WE_F : in std_logic; 96 I_WE_SR : in std_logic; 97 98 Q : out std_logic_vector ( 7 downto 0); 99 Q_CC : out std_logic); 100 end component; 101 102 signal S_FLAGS : std_logic_vector( 7 downto 0); 103 104 signal L_ADR : std_logic_vector(15 downto 0); 105 signal L_BASE : std_logic_vector(15 downto 0); 106 signal L_DDDD : std_logic_vector( 4 downto 1); 107 signal L_DSP : std_logic_vector(15 downto 0); 108 signal L_DX : std_logic_vector(15 downto 0); 109 signal L_DY : std_logic_vector(15 downto 0); 110 signal L_DZ : std_logic_vector(15 downto 0); 111 signal L_PRE : std_logic_vector(15 downto 0); 112 signal L_POST : std_logic_vector(15 downto 0); 113 signal L_S : std_logic_vector(15 downto 0); 114 signal L_WE_SP_AMOD : std_logic; 115 signal L_WE : std_logic_vector(31 downto 0); 116 signal L_WE_A : std_logic; 117 signal L_WE_D : std_logic_vector(31 downto 0); 118 signal L_WE_D2 : std_logic_vector( 1 downto 0); 119 signal L_WE_DD : std_logic_vector(31 downto 0); 120 signal L_WE_IO : std_logic_vector(31 downto 0); 121 signal L_WE_MISC : std_logic_vector(31 downto 0); 122 signal L_WE_X : std_logic; 123 signal L_WE_Y : std_logic; 124 signal L_WE_Z : std_logic; 125 signal L_WE_SP : std_logic_vector( 1 downto 0); 126 signal L_WE_SR : std_logic; 127 signal L_XYZS : std_logic_vector(15 downto 0); 128 129 begin 130 131 r00: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 1 downto 0), I_D => I_DIN, Q => R_R00); 132 r02: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 3 downto 2), I_D => I_DIN, Q => R_R02); 133 r04: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 5 downto 4), I_D => I_DIN, Q => R_R04); 134 r06: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 7 downto 6), I_D => I_DIN, Q => R_R06); 135 r08: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 9 downto 8), I_D => I_DIN, Q => R_R08); 136 r10: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(11 downto 10), I_D => I_DIN, Q => R_R10); 137 r12: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(13 downto 12), I_D => I_DIN, Q => R_R12); 138 r14: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(15 downto 14), I_D => I_DIN, Q => R_R14); 139 r16: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(17 downto 16), I_D => I_DIN, Q => R_R16); 140 r18: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(19 downto 18), I_D => I_DIN, Q => R_R18); 141 r20: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(21 downto 20), I_D => I_DIN, Q => R_R20); 142 r22: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(23 downto 22), I_D => I_DIN, Q => R_R22); 143 r24: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(25 downto 24), I_D => I_DIN, Q => R_R24); 144 r26: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(27 downto 26), I_D => L_DX, Q => R_R26); 145 r28: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(29 downto 28), I_D => L_DY, Q => R_R28); 146 r30: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(31 downto 30), I_D => L_DZ, Q => R_R30); 147 sp: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE_SP, I_D => L_DSP, Q => R_SP); 148 149 sr: status_reg 150 port map( I_CLK => I_CLK, 151 I_COND => I_COND, 152 I_DIN => I_DIN(7 downto 0), 153 I_FLAGS => I_FLAGS, 154 I_WE_F => I_WE_F, 155 I_WE_SR => L_WE_SR, 156 Q => S_FLAGS, 157 Q_CC => Q_CC); 158 159 -- The output of the register selected by L_ADR. 160 -- 161 process(R_R00, R_R02, R_R04, R_R06, R_R08, R_R10, R_R12, R_R14, 162 R_R16, R_R18, R_R20, R_R22, R_R24, R_R26, R_R28, R_R30, 163 R_SP, S_FLAGS, L_ADR(6 downto 1)) 164 begin 165 case L_ADR(6 downto 1) is 166 when "000000" => L_S <= R_R00; 167 when "000001" => L_S <= R_R02; 168 when "000010" => L_S <= R_R04; 169 when "000011" => L_S <= R_R06; 170 when "000100" => L_S <= R_R08; 171 when "000101" => L_S <= R_R10; 172 when "000110" => L_S <= R_R12; 173 when "000111" => L_S <= R_R14; 174 when "001000" => L_S <= R_R16; 175 when "001001" => L_S <= R_R18; 176 when "001010" => L_S <= R_R20; 177 when "001011" => L_S <= R_R22; 178 when "001100" => L_S <= R_R24; 179 when "001101" => L_S <= R_R26; 180 when "001110" => L_S <= R_R28; 181 when "001111" => L_S <= R_R30; 182 when "101111" => L_S <= R_SP ( 7 downto 0) & X"00"; -- SPL 183 when others => L_S <= S_FLAGS & R_SP (15 downto 8); -- SR/SPH 184 end case; 185 end process; 186 187 -- The output of the register pair selected by I_DDDDD. 188 -- 189 process(R_R00, R_R02, R_R04, R_R06, R_R08, R_R10, R_R12, R_R14, 190 R_R16, R_R18, R_R20, R_R22, R_R24, R_R26, R_R28, R_R30, 191 I_DDDDD(4 downto 1)) 192 begin 193 case I_DDDDD(4 downto 1) is 194 when "0000" => Q_D <= R_R00; 195 when "0001" => Q_D <= R_R02; 196 when "0010" => Q_D <= R_R04; 197 when "0011" => Q_D <= R_R06; 198 when "0100" => Q_D <= R_R08; 199 when "0101" => Q_D <= R_R10; 200 when "0110" => Q_D <= R_R12; 201 when "0111" => Q_D <= R_R14; 202 when "1000" => Q_D <= R_R16; 203 when "1001" => Q_D <= R_R18; 204 when "1010" => Q_D <= R_R20; 205 when "1011" => Q_D <= R_R22; 206 when "1100" => Q_D <= R_R24; 207 when "1101" => Q_D <= R_R26; 208 when "1110" => Q_D <= R_R28; 209 when others => Q_D <= R_R30; 210 end case; 211 end process; 212 213 -- The output of the register pair selected by I_RRRR. 214 -- 215 process(R_R00, R_R02, R_R04, R_R06, R_R08, R_R10, R_R12, R_R14, 216 R_R16, R_R18, R_R20, R_R22, R_R24, R_R26, R_R28, R_R30, I_RRRR) 217 begin 218 case I_RRRR is 219 when "0000" => Q_R <= R_R00; 220 when "0001" => Q_R <= R_R02; 221 when "0010" => Q_R <= R_R04; 222 when "0011" => Q_R <= R_R06; 223 when "0100" => Q_R <= R_R08; 224 when "0101" => Q_R <= R_R10; 225 when "0110" => Q_R <= R_R12; 226 when "0111" => Q_R <= R_R14; 227 when "1000" => Q_R <= R_R16; 228 when "1001" => Q_R <= R_R18; 229 when "1010" => Q_R <= R_R20; 230 when "1011" => Q_R <= R_R22; 231 when "1100" => Q_R <= R_R24; 232 when "1101" => Q_R <= R_R26; 233 when "1110" => Q_R <= R_R28; 234 when others => Q_R <= R_R30; 235 end case; 236 end process; 237 238 -- the base value of the X/Y/Z/SP register as per I_AMOD. 239 -- 240 process(I_AMOD(2 downto 0), I_IMM, R_SP, R_R26, R_R28, R_R30) 241 begin 242 case I_AMOD(2 downto 0) is 243 when AS_SP => L_BASE <= R_SP; 244 when AS_Z => L_BASE <= R_R30; 245 when AS_Y => L_BASE <= R_R28; 246 when AS_X => L_BASE <= R_R26; 247 when AS_IMM => L_BASE <= I_IMM; 248 when others => L_BASE <= X"0000"; 249 end case; 250 end process; 251 252 -- the value of the X/Y/Z/SP register after a potential PRE-decrement 253 -- (by 1 or 2) and POST-increment (by 1 or 2). 254 -- 255 process(I_AMOD(5 downto 3), I_IMM) 256 begin 257 case I_AMOD(5 downto 3) is 258 when AO_0 => L_PRE <= X"0000"; L_POST <= X"0000"; 259 when AO_i => L_PRE <= X"0000"; L_POST <= X"0001"; 260 when AO_ii => L_PRE <= X"0000"; L_POST <= X"0002"; 261 when AO_q => L_PRE <= I_IMM; L_POST <= X"0000"; 262 when AO_d => L_PRE <= X"FFFF"; L_POST <= X"FFFF"; 263 when AO_dd => L_PRE <= X"FFFE"; L_POST <= X"FFFE"; 264 when others => L_PRE <= X"0000"; L_POST <= X"0000"; 265 end case; 266 end process; 267 268 L_XYZS <= L_BASE + L_POST; 269 L_ADR <= L_BASE + L_PRE; 270 271 L_WE_A <= I_WE_M when (L_ADR(15 downto 5) = "00000000000") else '0'; 272 L_WE_SR <= I_WE_M when (L_ADR = X"005F") else '0'; 273 L_WE_SP_AMOD <= I_WE_XYZS when (I_AMOD(2 downto 0) = AS_SP) else '0'; 274 L_WE_SP(1) <= I_WE_M when (L_ADR = X"005E") else L_WE_SP_AMOD; 275 L_WE_SP(0) <= I_WE_M when (L_ADR = X"005D") else L_WE_SP_AMOD; 276 277 L_DX <= L_XYZS when (L_WE_MISC(26) = '1') else I_DIN; 278 L_DY <= L_XYZS when (L_WE_MISC(28) = '1') else I_DIN; 279 L_DZ <= L_XYZS when (L_WE_MISC(30) = '1') else I_DIN; 280 L_DSP <= L_XYZS when (I_AMOD(3 downto 0) = AM_WS) else I_DIN; 281 282 -- the WE signals for the differen registers. 283 -- 284 -- case 1: write to an 8-bit register addressed by DDDDD. 285 -- 286 -- I_WE_D(0) = '1' and I_DDDDD matches, 287 -- 288 L_WE_D( 0) <= I_WE_D(0) when (I_DDDDD = "00000") else '0'; 289 L_WE_D( 1) <= I_WE_D(0) when (I_DDDDD = "00001") else '0'; 290 L_WE_D( 2) <= I_WE_D(0) when (I_DDDDD = "00010") else '0'; 291 L_WE_D( 3) <= I_WE_D(0) when (I_DDDDD = "00011") else '0'; 292 L_WE_D( 4) <= I_WE_D(0) when (I_DDDDD = "00100") else '0'; 293 L_WE_D( 5) <= I_WE_D(0) when (I_DDDDD = "00101") else '0'; 294 L_WE_D( 6) <= I_WE_D(0) when (I_DDDDD = "00110") else '0'; 295 L_WE_D( 7) <= I_WE_D(0) when (I_DDDDD = "00111") else '0'; 296 L_WE_D( 8) <= I_WE_D(0) when (I_DDDDD = "01000") else '0'; 297 L_WE_D( 9) <= I_WE_D(0) when (I_DDDDD = "01001") else '0'; 298 L_WE_D(10) <= I_WE_D(0) when (I_DDDDD = "01010") else '0'; 299 L_WE_D(11) <= I_WE_D(0) when (I_DDDDD = "01011") else '0'; 300 L_WE_D(12) <= I_WE_D(0) when (I_DDDDD = "01100") else '0'; 301 L_WE_D(13) <= I_WE_D(0) when (I_DDDDD = "01101") else '0'; 302 L_WE_D(14) <= I_WE_D(0) when (I_DDDDD = "01110") else '0'; 303 L_WE_D(15) <= I_WE_D(0) when (I_DDDDD = "01111") else '0'; 304 L_WE_D(16) <= I_WE_D(0) when (I_DDDDD = "10000") else '0'; 305 L_WE_D(17) <= I_WE_D(0) when (I_DDDDD = "10001") else '0'; 306 L_WE_D(18) <= I_WE_D(0) when (I_DDDDD = "10010") else '0'; 307 L_WE_D(19) <= I_WE_D(0) when (I_DDDDD = "10011") else '0'; 308 L_WE_D(20) <= I_WE_D(0) when (I_DDDDD = "10100") else '0'; 309 L_WE_D(21) <= I_WE_D(0) when (I_DDDDD = "10101") else '0'; 310 L_WE_D(22) <= I_WE_D(0) when (I_DDDDD = "10110") else '0'; 311 L_WE_D(23) <= I_WE_D(0) when (I_DDDDD = "10111") else '0'; 312 L_WE_D(24) <= I_WE_D(0) when (I_DDDDD = "11000") else '0'; 313 L_WE_D(25) <= I_WE_D(0) when (I_DDDDD = "11001") else '0'; 314 L_WE_D(26) <= I_WE_D(0) when (I_DDDDD = "11010") else '0'; 315 L_WE_D(27) <= I_WE_D(0) when (I_DDDDD = "11011") else '0'; 316 L_WE_D(28) <= I_WE_D(0) when (I_DDDDD = "11100") else '0'; 317 L_WE_D(29) <= I_WE_D(0) when (I_DDDDD = "11101") else '0'; 318 L_WE_D(30) <= I_WE_D(0) when (I_DDDDD = "11110") else '0'; 319 L_WE_D(31) <= I_WE_D(0) when (I_DDDDD = "11111") else '0'; 320 321 -- 322 -- case 2: write to a 16-bit register pair addressed by DDDD. 323 -- 324 -- I_WE_DD(1) = '1' and L_DDDD matches, 325 -- 326 L_DDDD <= I_DDDDD(4 downto 1); 327 L_WE_D2 <= I_WE_D(1) & I_WE_D(1); 328 L_WE_DD( 1 downto 0) <= L_WE_D2 when (L_DDDD = "0000") else "00"; 329 L_WE_DD( 3 downto 2) <= L_WE_D2 when (L_DDDD = "0001") else "00"; 330 L_WE_DD( 5 downto 4) <= L_WE_D2 when (L_DDDD = "0010") else "00"; 331 L_WE_DD( 7 downto 6) <= L_WE_D2 when (L_DDDD = "0011") else "00"; 332 L_WE_DD( 9 downto 8) <= L_WE_D2 when (L_DDDD = "0100") else "00"; 333 L_WE_DD(11 downto 10) <= L_WE_D2 when (L_DDDD = "0101") else "00"; 334 L_WE_DD(13 downto 12) <= L_WE_D2 when (L_DDDD = "0110") else "00"; 335 L_WE_DD(15 downto 14) <= L_WE_D2 when (L_DDDD = "0111") else "00"; 336 L_WE_DD(17 downto 16) <= L_WE_D2 when (L_DDDD = "1000") else "00"; 337 L_WE_DD(19 downto 18) <= L_WE_D2 when (L_DDDD = "1001") else "00"; 338 L_WE_DD(21 downto 20) <= L_WE_D2 when (L_DDDD = "1010") else "00"; 339 L_WE_DD(23 downto 22) <= L_WE_D2 when (L_DDDD = "1011") else "00"; 340 L_WE_DD(25 downto 24) <= L_WE_D2 when (L_DDDD = "1100") else "00"; 341 L_WE_DD(27 downto 26) <= L_WE_D2 when (L_DDDD = "1101") else "00"; 342 L_WE_DD(29 downto 28) <= L_WE_D2 when (L_DDDD = "1110") else "00"; 343 L_WE_DD(31 downto 30) <= L_WE_D2 when (L_DDDD = "1111") else "00"; 344 345 -- 346 -- case 3: write to an 8-bit register pair addressed by an I/O address. 347 -- 348 -- L_WE_A = '1' and L_ADR(4 downto 0) matches 349 -- 350 L_WE_IO( 0) <= L_WE_A when (L_ADR(4 downto 0) = "00000") else '0'; 351 L_WE_IO( 1) <= L_WE_A when (L_ADR(4 downto 0) = "00001") else '0'; 352 L_WE_IO( 2) <= L_WE_A when (L_ADR(4 downto 0) = "00010") else '0'; 353 L_WE_IO( 3) <= L_WE_A when (L_ADR(4 downto 0) = "00011") else '0'; 354 L_WE_IO( 4) <= L_WE_A when (L_ADR(4 downto 0) = "00100") else '0'; 355 L_WE_IO( 5) <= L_WE_A when (L_ADR(4 downto 0) = "00101") else '0'; 356 L_WE_IO( 6) <= L_WE_A when (L_ADR(4 downto 0) = "00110") else '0'; 357 L_WE_IO( 7) <= L_WE_A when (L_ADR(4 downto 0) = "00111") else '0'; 358 L_WE_IO( 8) <= L_WE_A when (L_ADR(4 downto 0) = "01000") else '0'; 359 L_WE_IO( 9) <= L_WE_A when (L_ADR(4 downto 0) = "01001") else '0'; 360 L_WE_IO(10) <= L_WE_A when (L_ADR(4 downto 0) = "01010") else '0'; 361 L_WE_IO(11) <= L_WE_A when (L_ADR(4 downto 0) = "01011") else '0'; 362 L_WE_IO(12) <= L_WE_A when (L_ADR(4 downto 0) = "01100") else '0'; 363 L_WE_IO(13) <= L_WE_A when (L_ADR(4 downto 0) = "01101") else '0'; 364 L_WE_IO(14) <= L_WE_A when (L_ADR(4 downto 0) = "01110") else '0'; 365 L_WE_IO(15) <= L_WE_A when (L_ADR(4 downto 0) = "01111") else '0'; 366 L_WE_IO(16) <= L_WE_A when (L_ADR(4 downto 0) = "10000") else '0'; 367 L_WE_IO(17) <= L_WE_A when (L_ADR(4 downto 0) = "10001") else '0'; 368 L_WE_IO(18) <= L_WE_A when (L_ADR(4 downto 0) = "10010") else '0'; 369 L_WE_IO(19) <= L_WE_A when (L_ADR(4 downto 0) = "10011") else '0'; 370 L_WE_IO(20) <= L_WE_A when (L_ADR(4 downto 0) = "10100") else '0'; 371 L_WE_IO(21) <= L_WE_A when (L_ADR(4 downto 0) = "10101") else '0'; 372 L_WE_IO(22) <= L_WE_A when (L_ADR(4 downto 0) = "10110") else '0'; 373 L_WE_IO(23) <= L_WE_A when (L_ADR(4 downto 0) = "10111") else '0'; 374 L_WE_IO(24) <= L_WE_A when (L_ADR(4 downto 0) = "11000") else '0'; 375 L_WE_IO(25) <= L_WE_A when (L_ADR(4 downto 0) = "11001") else '0'; 376 L_WE_IO(26) <= L_WE_A when (L_ADR(4 downto 0) = "11010") else '0'; 377 L_WE_IO(27) <= L_WE_A when (L_ADR(4 downto 0) = "11011") else '0'; 378 L_WE_IO(28) <= L_WE_A when (L_ADR(4 downto 0) = "11100") else '0'; 379 L_WE_IO(29) <= L_WE_A when (L_ADR(4 downto 0) = "11101") else '0'; 380 L_WE_IO(30) <= L_WE_A when (L_ADR(4 downto 0) = "11110") else '0'; 381 L_WE_IO(31) <= L_WE_A when (L_ADR(4 downto 0) = "11111") else '0'; 382 383 -- case 4 special cases. 384 -- 4a. WE_01 for register pair 0/1 (multiplication opcode). 385 -- 4b. I_WE_XYZS for X (register pairs 26/27) and I_AMOD matches 386 -- 4c. I_WE_XYZS for Y (register pairs 28/29) and I_AMOD matches 387 -- 4d. I_WE_XYZS for Z (register pairs 30/31) and I_AMOD matches 388 -- 389 L_WE_X <= I_WE_XYZS when (I_AMOD(3 downto 0) = AM_WX) else '0'; 390 L_WE_Y <= I_WE_XYZS when (I_AMOD(3 downto 0) = AM_WY) else '0'; 391 L_WE_Z <= I_WE_XYZS when (I_AMOD(3 downto 0) = AM_WZ) else '0'; 392 L_WE_MISC <= L_WE_Z & L_WE_Z & -- -Z and Z+ address modes r30 393 L_WE_Y & L_WE_Y & -- -Y and Y+ address modes r28 394 L_WE_X & L_WE_X & -- -X and X+ address modes r26 395 X"000000" & -- never r24 - r02 396 I_WE_01 & I_WE_01; -- multiplication result r00 397 398 L_WE <= L_WE_D or L_WE_DD or L_WE_IO or L_WE_MISC; 399 400 Q_S <= L_S( 7 downto 0) when (L_ADR(0) = '0') else L_S(15 downto 8); 401 Q_FLAGS <= S_FLAGS; 402 Q_Z <= R_R30; 403 Q_ADR <= L_ADR; 404 405 end Behavioral; 406 <pre class="filename"> src/register_file.vhd </pre></pre> <P> <P><hr><BR> <table class="ttop"><th class="tpre"><a href="22_Listing_of_reg_16.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="24_Listing_of_segment7.vhd.html">Next Lesson</a></th></table> </BODY> </HTML>