URL
https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk
Subversion Repositories cpu_lecture
[/] [cpu_lecture/] [trunk/] [html/] [25_Listing_of_status_reg.vhd.html] - Rev 2
Compare with Previous | Blame | View Log
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <HTML> <HEAD> <TITLE>html/Listing_of_status_reg.vhd</TITLE> <META NAME="generator" CONTENT="HTML::TextToHTML v2.46"> <LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css"> </HEAD> <BODY> <P><table class="ttop"><th class="tpre"><a href="24_Listing_of_segment7.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="26_Listing_of_uart_rx.vhd.html">Next Lesson</a></th></table> <hr> <H1><A NAME="section_1">25 LISTING OF status_reg.vhd</A></H1> <pre class="vhdl"> 1 ------------------------------------------------------------------------------- 2 -- 3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann 4 -- 5 -- This code is free software: you can redistribute it and/or modify 6 -- it under the terms of the GNU General Public License as published by 7 -- the Free Software Foundation, either version 3 of the License, or 8 -- (at your option) any later version. 9 -- 10 -- This code is distributed in the hope that it will be useful, 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 -- GNU General Public License for more details. 14 -- 15 -- You should have received a copy of the GNU General Public License 16 -- along with this code (see the file named COPYING). 17 -- If not, see http://www.gnu.org/licenses/. 18 -- 19 ------------------------------------------------------------------------------- 20 ------------------------------------------------------------------------------- 21 -- 22 -- Module Name: Register - Behavioral 23 -- Create Date: 16:15:54 12/26/2009 24 -- Description: the status register of a CPU. 25 -- 26 ---------------------------------------------------------------------------------- 27 library IEEE; 28 use IEEE.STD_LOGIC_1164.ALL; 29 use IEEE.STD_LOGIC_ARITH.ALL; 30 use IEEE.STD_LOGIC_UNSIGNED.ALL; 31 32 entity status_reg is 33 port ( I_CLK : in std_logic; 34 35 I_COND : in std_logic_vector ( 3 downto 0); 36 I_DIN : in std_logic_vector ( 7 downto 0); 37 I_FLAGS : in std_logic_vector ( 7 downto 0); 38 I_WE_F : in std_logic; 39 I_WE_SR : in std_logic; 40 41 Q : out std_logic_vector ( 7 downto 0); 42 Q_CC : out std_logic); 43 end status_reg; 44 45 architecture Behavioral of status_reg is 46 47 signal L : std_logic_vector ( 7 downto 0); 48 begin 49 50 process(I_CLK) 51 begin 52 if (rising_edge(I_CLK)) then 53 if (I_WE_F = '1') then -- write flags (from ALU) 54 L <= I_FLAGS; 55 elsif (I_WE_SR = '1') then -- write I/O 56 L <= I_DIN; 57 end if; 58 end if; 59 end process; 60 61 cond: process(I_COND, L) 62 begin 63 case I_COND(2 downto 0) is 64 when "000" => Q_CC <= L(0) xor I_COND(3); 65 when "001" => Q_CC <= L(1) xor I_COND(3); 66 when "010" => Q_CC <= L(2) xor I_COND(3); 67 when "011" => Q_CC <= L(3) xor I_COND(3); 68 when "100" => Q_CC <= L(4) xor I_COND(3); 69 when "101" => Q_CC <= L(5) xor I_COND(3); 70 when "110" => Q_CC <= L(6) xor I_COND(3); 71 when others => Q_CC <= L(7) xor I_COND(3); 72 end case; 73 end process; 74 75 Q <= L; 76 77 end Behavioral; 78 <pre class="filename"> src/status_reg.vhd </pre></pre> <P> <P><hr><BR> <table class="ttop"><th class="tpre"><a href="24_Listing_of_segment7.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="26_Listing_of_uart_rx.vhd.html">Next Lesson</a></th></table> </BODY> </HTML>