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<H1><A NAME="section_1">27 LISTING OF uart_tx.vhd</A></H1>
 
<pre class="vhdl">
 
  1	-------------------------------------------------------------------------------
  2	-- 
  3	-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
  4	-- 
  5	--  This code is free software: you can redistribute it and/or modify
  6	--  it under the terms of the GNU General Public License as published by
  7	--  the Free Software Foundation, either version 3 of the License, or
  8	--  (at your option) any later version.
  9	--
 10	--  This code is distributed in the hope that it will be useful,
 11	--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 12	--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13	--  GNU General Public License for more details.
 14	--
 15	--  You should have received a copy of the GNU General Public License
 16	--  along with this code (see the file named COPYING).
 17	--  If not, see http://www.gnu.org/licenses/.
 18	--
 19	-------------------------------------------------------------------------------
 20	-------------------------------------------------------------------------------
 21	--
 22	-- Module Name:    uart_tx - Behavioral 
 23	-- Create Date:    14:21:59 11/07/2009 
 24	-- Description:    a UART receiver.
 25	--
 26	-------------------------------------------------------------------------------
 27	--
 28	library IEEE;
 29	use IEEE.STD_LOGIC_1164.ALL;
 30	use IEEE.STD_LOGIC_ARITH.ALL;
 31	use IEEE.STD_LOGIC_UNSIGNED.ALL;
 32	
 33	entity uart_tx is 
 34	    port(   I_CLK       : in  std_logic;    
 35	            I_CLR       : in  std_logic;            -- RESET
 36	            I_CE_1      : in  std_logic;            -- BAUD rate clock enable
 37	            I_DATA      : in  std_logic_vector(7 downto 0);   -- DATA to be sent
 38	            I_FLAG      : in  std_logic;            -- toggle to send data
 39	            Q_TX        : out std_logic;            -- Serial output line
 40	            Q_FLAG      : out std_logic);           -- Transmitting Flag
 41	end uart_tx;
 42	 
 43	architecture Behavioral of uart_tx is
 44	 
 45	signal L_BUF            : std_logic_vector(7 downto 0);
 46	signal L_TODO           : std_logic_vector(3 downto 0);     -- bits to send
 47	signal L_FLAG           : std_logic;
 48	 
 49	begin
 50	 
 51	    process(I_CLK)
 52	    begin
 53	        if (rising_edge(I_CLK)) then
 54	            if (I_CLR = '1') then
 55	                Q_TX   <= '1';
 56	                L_BUF  <= "11111111";
 57	                L_TODO <= "0000";
 58	                L_FLAG <= I_FLAG;                   -- idle
 59	            elsif (I_CE_1 = '1') then
 60	                if (L_TODO /= "0000") then          -- transmitting
 61	                    Q_TX <= L_BUF(0);               -- next bit
 62	                    L_BUF     <= '1' & L_BUF(7 downto 1);
 63	                    if (L_TODO = "0001") then
 64	                        L_FLAG <= I_FLAG;
 65	                    end if;
 66	                    L_TODO <= L_TODO - "0001";
 67	                elsif (L_FLAG /= I_FLAG) then       -- new byte
 68	                    Q_TX <= '0';                    -- start bit
 69	                    L_BUF <= I_DATA;                -- data bits
 70	                    L_TODO <= "1001";
 71	                end if;
 72	            end if;
 73	        end if;
 74	    end process; 
 75	 
 76	    Q_FLAG <= L_FLAG;
 77	 
 78	end Behavioral;  
 79	 
<pre class="filename">
src/uart_tx.vhd
</pre></pre>
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