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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <HTML> <HEAD> <TITLE>html/Listing_of_test_tb.vhd</TITLE> <META NAME="generator" CONTENT="HTML::TextToHTML v2.46"> <LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css"> </HEAD> <BODY> <P><table class="ttop"><th class="tpre"><a href="28_Listing_of_RAMB4_S4_S4.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="30_Listing_of_avr_fpga.ucf.html">Next Lesson</a></th></table> <hr> <H1><A NAME="section_1">29 LISTING OF test_tb.vhd</A></H1> <pre class="vhdl"> 1 ------------------------------------------------------------------------------- 2 -- 3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann 4 -- 5 -- This code is free software: you can redistribute it and/or modify 6 -- it under the terms of the GNU General Public License as published by 7 -- the Free Software Foundation, either version 3 of the License, or 8 -- (at your option) any later version. 9 -- 10 -- This code is distributed in the hope that it will be useful, 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 -- GNU General Public License for more details. 14 -- 15 -- You should have received a copy of the GNU General Public License 16 -- along with this code (see the file named COPYING). 17 -- If not, see http://www.gnu.org/licenses/. 18 -- 19 ------------------------------------------------------------------------------- 20 ------------------------------------------------------------------------------- 21 -- 22 -- Module Name: alu - Behavioral 23 -- Create Date: 16:47:24 12/29/2009 24 -- Description: arithmetic logic unit of a CPU 25 -- 26 ------------------------------------------------------------------------------- 27 -- 28 library IEEE; 29 use IEEE.STD_LOGIC_1164.ALL; 30 use IEEE.STD_LOGIC_ARITH.ALL; 31 use IEEE.STD_LOGIC_UNSIGNED.ALL; 32 33 entity testbench is 34 end testbench; 35 36 architecture Behavioral of testbench is 37 38 component avr_fpga 39 port ( I_CLK_100 : in std_logic; 40 I_SWITCH : in std_logic_vector(9 downto 0); 41 I_RX : in std_logic; 42 43 Q_7_SEGMENT : out std_logic_vector(6 downto 0); 44 Q_LEDS : out std_logic_vector(3 downto 0); 45 Q_TX : out std_logic); 46 end component; 47 48 signal L_CLK_100 : std_logic; 49 signal L_LEDS : std_logic_vector(3 downto 0); 50 signal L_7_SEGMENT : std_logic_vector(6 downto 0); 51 signal L_RX : std_logic; 52 signal L_SWITCH : std_logic_vector(9 downto 0); 53 signal L_TX : std_logic; 54 55 signal L_CLK_COUNT : integer := 0; 56 57 begin 58 59 fpga: avr_fpga 60 port map( I_CLK_100 => L_CLK_100, 61 I_SWITCH => L_SWITCH, 62 I_RX => L_RX, 63 64 Q_LEDS => L_LEDS, 65 Q_7_SEGMENT => L_7_SEGMENT, 66 Q_TX => L_TX); 67 68 process -- clock process for CLK_100, 69 begin 70 clock_loop : loop 71 L_CLK_100 <= transport '0'; 72 wait for 5 ns; 73 74 L_CLK_100 <= transport '1'; 75 wait for 5 ns; 76 end loop clock_loop; 77 end process; 78 79 process(L_CLK_100) 80 begin 81 if (rising_edge(L_CLK_100)) then 82 case L_CLK_COUNT is 83 when 0 => L_SWITCH <= "0011100000"; L_RX <= '0'; 84 when 2 => L_SWITCH(9 downto 8) <= "11"; 85 when others => 86 end case; 87 L_CLK_COUNT <= L_CLK_COUNT + 1; 88 end if; 89 end process; 90 end Behavioral; 91 <pre class="filename"> test/test_tb.vhd </pre></pre> <P> <P><hr><BR> <table class="ttop"><th class="tpre"><a href="28_Listing_of_RAMB4_S4_S4.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="30_Listing_of_avr_fpga.ucf.html">Next Lesson</a></th></table> </BODY> </HTML>