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<H1><A NAME="section_1">31 LISTING OF Makefile</A></H1>
 
<pre class="vhdl">
 
  1	PROJECT=avr_core
  2	
  3	# the vhdl source files (except testbench)
  4	#
  5	FILES		+= src/*.vhd
  6	
  7	# the testbench sources and binary.
  8	#
  9	SIMFILES	= test/test_tb.vhd test/RAMB4_S4_S4.vhd
 10	SIMTOP		= testbench
 11	
 12	# When to stop the simulation
 13	#
 14	# GHDL_SIM_OPT	= --assert-level=error
 15	GHDL_SIM_OPT	= --stop-time=40us
 16	
 17	SIMDIR		= simu
 18	
 19	FLAGS		= --ieee=synopsys --warn-no-vital-generic -fexplicit --std=93c
 20	
 21	all:
 22		make compile
 23		make run 2>& 1 | grep -v std_logic_arith
 24		make view
 25	
 26	compile:
 27		@mkdir -p simu
 28		@echo -----------------------------------------------------------------
 29		ghdl -i $(FLAGS) --workdir=simu --work=work $(SIMFILES) $(FILES)
 30		@echo
 31		@echo -----------------------------------------------------------------
 32		ghdl -m $(FLAGS) --workdir=simu --work=work $(SIMTOP)
 33		@echo
 34		@mv $(SIMTOP) simu/$(SIMTOP)
 35	
 36	run:
 37		@$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
 38	
 39	view:
 40		gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | gtkwave --vcd gtkwave.save
 41	
 42	clean:
 43		ghdl --clean --workdir=simu
 44	
<pre class="filename">
Makefile
</pre></pre>
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