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[/] [dma_axi/] [trunk/] [src/] [dma_axi64/] [prgen_delay.v] - Rev 4
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///////////////////////////////////////////////////////////////////// //// //// //// Author: Eyal Hochberg //// //// eyal@provartec.com //// //// //// //// Downloaded from: http://www.opencores.org //// ///////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Provartec LTD //// //// www.provartec.com //// //// info@provartec.com //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer.//// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation.//// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more//// //// details. http://www.gnu.org/licenses/lgpl.html //// //// //// ///////////////////////////////////////////////////////////////////// //--------------------------------------------------------- //-- File generated by RobustVerilog parser //-- Version: 1.0 //-- Invoked Fri Mar 25 23:36:57 2011 //-- //-- Source file: prgen_delay.v //--------------------------------------------------------- module prgen_delay(clk,reset,din,dout); input clk; input reset; input din; output dout; parameter DELAY = 2; reg [DELAY:0] shift_reg; always @(posedge clk or posedge reset) if (reset) shift_reg <= #1 {DELAY+1{1'b0}}; else shift_reg <= #1 {shift_reg[DELAY-1:0], din}; assign dout = shift_reg[DELAY-1]; endmodule