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[/] [dp_repack_data/] [trunk/] [tb_dp_repack_data.vhd] - Rev 5
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------------------------------------------------------------------------------- -- -- Copyright 2020 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ------------------------------------------------------------------------------- -- Purpose: -- . Test bench for dp_repack_data -- Description: -- c_no_unpack -- . -- g_in_dat_w g_pack_dat_w . g_in_dat_w -- g_in_nof_words g_pack_nof_words . g_in_nof_words -- . . . . -- . u_pack . u_unpack . . -- . ______________ . ______________ . -- . |dp_repack_data| . |dp_repack_data| . -- stimuli_src ---->| |----------->| |----> verify_snk -- | in out | pack_src | in out | -- |______________| |______________| -- -- Usage: -- > as 10 -- > run -all -- LIBRARY IEEE, common_pkg_lib, dp_pkg_lib; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; USE common_pkg_lib.common_pkg.ALL; USE common_pkg_lib.common_lfsr_sequences_pkg.ALL; USE common_pkg_lib.tb_common_pkg.ALL; USE dp_pkg_lib.dp_stream_pkg.ALL; USE dp_pkg_lib.tb_dp_pkg.ALL; ENTITY tb_dp_repack_data IS GENERIC ( -- general g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control -- specific g_in_dat_w : NATURAL := 8 * 42; g_in_nof_words : NATURAL := 1; g_pack_dat_w : NATURAL := 32; g_pack_nof_words : NATURAL := 11; g_in_bypass : BOOLEAN := TRUE; -- can use TRUE when g_in_nof_words=1 or g_in_nof_words=g_out_nof_words g_pack_bypass : BOOLEAN := FALSE; -- can use TRUE when g_out_nof_words=1 or g_in_nof_words=g_out_nof_words g_in_symbol_w : NATURAL := 8; -- default 1 for snk_in.empty in nof bits, else use power of 2 g_pack_symbol_w : NATURAL := 8; -- default 1 for src_out.empty in nof bits, else use power of 2 g_nof_repeat : NATURAL := 10; g_pkt_len : NATURAL := 1; -- if not a multiple of g_in_nof_words then the input stage flush creates gap between blocks g_pkt_gap : NATURAL := 0 ); END tb_dp_repack_data; ARCHITECTURE tb OF tb_dp_repack_data IS CONSTANT c_no_unpack : BOOLEAN := FALSE; CONSTANT c_enable_repack_in : BOOLEAN := TRUE; CONSTANT c_enable_repack_out : BOOLEAN := TRUE; -- dp_stream_stimuli CONSTANT c_stimuli_pulse_active : NATURAL := 3; --g_in_nof_words; CONSTANT c_stimuli_pulse_period : NATURAL := 7; CONSTANT c_data_init : NATURAL := 0; CONSTANT c_bsn_init : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := X"0000000000000000"; -- X"0877665544332211" CONSTANT c_err_init : NATURAL := 247; CONSTANT c_channel_init : NATURAL := 5; -- fixed -- dp_stream_verify CONSTANT c_verify_pulse_active : NATURAL := 1; CONSTANT c_verify_pulse_period : NATURAL := 5; CONSTANT c_data_max : UNSIGNED(g_in_dat_w-1 DOWNTO 0) := (OTHERS=>'1'); CONSTANT c_dsp_max : UNSIGNED(g_in_dat_w-1 DOWNTO 0) := (OTHERS=>'1'); --CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0); CONSTANT c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1 CONSTANT c_expected_pkt_len : NATURAL := sel_a_b(c_no_unpack, g_pkt_len * g_pack_nof_words / g_in_nof_words, g_pkt_len); -- both CONSTANT c_sync_period : NATURAL := 10; CONSTANT c_sync_offset : NATURAL := 7; SIGNAL clk : STD_LOGIC := '1'; SIGNAL rst : STD_LOGIC := '1'; SIGNAL tb_end : STD_LOGIC := '0'; SIGNAL stimuli_src_in : t_dp_siso := c_dp_siso_rdy; SIGNAL stimuli_src_out : t_dp_sosi; SIGNAL stimuli_src_out_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0); SIGNAL verify_snk_in_enable : t_dp_sosi_sl := c_dp_sosi_sl_rst; SIGNAL last_snk_in : t_dp_sosi; SIGNAL last_snk_in_evt : STD_LOGIC; SIGNAL verify_last_snk_in_evt : t_dp_sosi_sl := c_dp_sosi_sl_rst; SIGNAL verify_snk_out : t_dp_siso := c_dp_siso_rdy; SIGNAL verify_snk_in : t_dp_sosi; SIGNAL verify_snk_in_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0); -- specific SIGNAL pack_src_in : t_dp_siso; SIGNAL pack_src_out : t_dp_sosi; SIGNAL pack_src_out_data : STD_LOGIC_VECTOR(g_pack_dat_w-1 DOWNTO 0); SIGNAL unpack_src_in : t_dp_siso; SIGNAL unpack_src_out : t_dp_sosi; SIGNAL unpack_src_out_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0); BEGIN clk <= (NOT clk) OR tb_end AFTER clk_period/2; rst <= '1', '0' AFTER clk_period*7; ------------------------------------------------------------------------------ -- DATA GENERATION ------------------------------------------------------------------------------ u_dp_stream_stimuli : ENTITY dp_pkg_lib.dp_stream_stimuli GENERIC MAP ( g_instance_nr => 0, -- only one stream so choose index 0 -- flow control g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences g_pulse_active => c_stimuli_pulse_active, g_pulse_period => c_stimuli_pulse_period, g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control -- initializations g_sync_period => c_sync_period, g_sync_offset => c_sync_offset, g_data_init => c_data_init, g_bsn_init => c_bsn_init, g_err_init => c_err_init, g_channel_init => c_channel_init, -- specific g_in_dat_w => g_in_dat_w, g_nof_repeat => g_nof_repeat, g_pkt_len => g_pkt_len, g_pkt_gap => g_pkt_gap ) PORT MAP ( rst => rst, clk => clk, -- Generate stimuli src_in => stimuli_src_in, src_out => stimuli_src_out, -- End of stimuli last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned ); ------------------------------------------------------------------------------ -- DATA VERIFICATION ------------------------------------------------------------------------------ -- Select fields that need to be verified -- . during the test verify_snk_in_enable.sync <= '1'; verify_snk_in_enable.bsn <= '1'; verify_snk_in_enable.data <= '1' WHEN c_no_unpack=FALSE ELSE '0'; verify_snk_in_enable.re <= '0'; verify_snk_in_enable.im <= '0'; verify_snk_in_enable.valid <= '1'; verify_snk_in_enable.sop <= '1'; verify_snk_in_enable.eop <= '1'; verify_snk_in_enable.empty <= '0'; verify_snk_in_enable.channel <= '1'; verify_snk_in_enable.err <= '1'; -- . after the test verify_last_snk_in_evt.sync <= last_snk_in_evt; verify_last_snk_in_evt.bsn <= last_snk_in_evt; verify_last_snk_in_evt.data <= last_snk_in_evt WHEN c_no_unpack=FALSE ELSE '0'; verify_last_snk_in_evt.re <= '0'; verify_last_snk_in_evt.im <= '0'; verify_last_snk_in_evt.valid <= last_snk_in_evt; verify_last_snk_in_evt.sop <= last_snk_in_evt; verify_last_snk_in_evt.eop <= last_snk_in_evt; verify_last_snk_in_evt.empty <= '0'; verify_last_snk_in_evt.channel <= last_snk_in_evt; verify_last_snk_in_evt.err <= last_snk_in_evt; u_dp_stream_verify : ENTITY dp_pkg_lib.dp_stream_verify GENERIC MAP ( g_instance_nr => 0, -- only one stream so choose index 0 -- flow control g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences g_pulse_active => c_verify_pulse_active, g_pulse_period => c_verify_pulse_period, g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control -- initializations g_sync_period => c_sync_period, g_sync_offset => c_sync_offset, g_snk_in_cnt_max => c_verify_snk_in_cnt_max, g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap, -- specific g_in_dat_w => g_in_dat_w, g_pkt_len => c_expected_pkt_len ) PORT MAP ( rst => rst, clk => clk, -- Verify data snk_out => verify_snk_out, snk_in => verify_snk_in, -- During stimuli verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing -- End of stimuli expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in ); ------------------------------------------------------------------------------ -- DUT Pack ------------------------------------------------------------------------------ u_pack : ENTITY work.dp_repack_data GENERIC MAP ( g_enable_repack_in => c_enable_repack_in, g_enable_repack_out => c_enable_repack_out, g_in_bypass => g_in_bypass, g_in_dat_w => g_in_dat_w, g_in_nof_words => g_in_nof_words, g_in_symbol_w => g_in_symbol_w, g_out_bypass => g_pack_bypass, g_out_dat_w => g_pack_dat_w, g_out_nof_words => g_pack_nof_words, g_out_symbol_w => g_pack_symbol_w ) PORT MAP ( rst => rst, clk => clk, snk_out => stimuli_src_in, snk_in => stimuli_src_out, src_in => pack_src_in, src_out => pack_src_out ); pack_src_out_data <= pack_src_out.data(g_pack_dat_w-1 DOWNTO 0); ------------------------------------------------------------------------------ -- DUT Unpack ------------------------------------------------------------------------------ no_unpack : IF c_no_unpack=TRUE GENERATE pack_src_in <= unpack_src_in; unpack_src_out <= pack_src_out; END GENERATE; gen_unpack : IF c_no_unpack=FALSE GENERATE u_unpack : ENTITY work.dp_repack_data GENERIC MAP ( g_enable_repack_in => c_enable_repack_out, g_enable_repack_out => c_enable_repack_in, g_in_bypass => g_pack_bypass, g_in_dat_w => g_pack_dat_w, g_in_nof_words => g_pack_nof_words, g_in_symbol_w => g_pack_symbol_w, g_out_bypass => g_in_bypass, g_out_dat_w => g_in_dat_w, g_out_nof_words => g_in_nof_words, g_out_symbol_w => g_in_symbol_w ) PORT MAP ( rst => rst, clk => clk, snk_out => pack_src_in, snk_in => pack_src_out, src_in => unpack_src_in, src_out => unpack_src_out ); END GENERATE; unpack_src_out_data <= unpack_src_out.data(g_in_dat_w-1 DOWNTO 0); unpack_src_in <= verify_snk_out; verify_snk_in <= unpack_src_out; ------------------------------------------------------------------------------ -- Auxiliary ------------------------------------------------------------------------------ -- Map to slv to ease monitoring in wave window stimuli_src_out_data <= stimuli_src_out.data(g_in_dat_w-1 DOWNTO 0); verify_snk_in_data <= verify_snk_in.data(g_in_dat_w-1 DOWNTO 0); END tb;