URL
https://opencores.org/ocsvn/mblite/mblite/trunk
Subversion Repositories mblite
[/] [mblite/] [trunk/] [designs/] [core_syn/] [sram_init.vhd] - Rev 6
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---------------------------------------------------------------------------------------------- -- -- Input file : sram_init.vhd -- Design name : sram_init -- Author : Tamar Kranenburg -- Company : Delft University of Technology -- : Faculty EEMCS, Department ME&CE -- : Systems and Circuits group -- -- Description : Single Port Synchronous Random Access Memory -- ---------------------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; LIBRARY mblite; USE mblite.std_Pkg.ALL; ENTITY sram_init IS GENERIC ( WIDTH : integer := 32; SIZE : integer := 11 ); PORT ( dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0); dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0); adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0); wre_i : IN std_logic; ena_i : IN std_logic; clk_i : IN std_logic ); END sram_init; ARCHITECTURE arch OF sram_init IS TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_logic_vector(WIDTH - 1 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X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000", X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000", X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000", X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000", X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000", X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000", X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000"); BEGIN PROCESS(clk_i) BEGIN IF rising_edge(clk_i) THEN IF notx(adr_i) AND ena_i = '1' THEN IF wre_i = '1' THEN ram(my_conv_integer(adr_i)) <= dat_i; END IF; dat_o <= ram(my_conv_integer(adr_i)); END IF; END IF; END PROCESS; END arch;
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