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[/] [mesi_isc/] [trunk/] [syn/] [mesi_isc.map.rpt] - Rev 4

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Analysis & Synthesis report for mesi_isc
Tue Dec 25 13:54:13 2012
Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Parameter Settings for User Entity Instance: Top-level Entity: |mesi_isc
 12. Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad
 13. Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl
 14. Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo
 15. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos
 16. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl
 17. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3
 18. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2
 19. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1
 20. Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0
 21. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0"
 22. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1"
 23. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2"
 24. Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"
 25. Port Connectivity Checks: "mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl"
 26. Elapsed Time Per Partition
 27. Analysis & Synthesis Messages
 28. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Dec 25 13:54:13 2012         ;
; Quartus II 32-bit Version          ; 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition ;
; Revision Name                      ; mesi_isc                                      ;
; Top-level Entity Name              ; mesi_isc                                      ;
; Family                             ; Cyclone IV GX                                 ;
; Total logic elements               ; 863                                           ;
;     Total combinational functions  ; 481                                           ;
;     Dedicated logic registers      ; 636                                           ;
; Total registers                    ; 636                                           ;
; Total pins                         ; 194                                           ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 0                                             ;
; Embedded Multiplier 9-bit elements ; 0                                             ;
; Total GXB Receiver Channel PCS     ; 0                                             ;
; Total GXB Receiver Channel PMA     ; 0                                             ;
; Total GXB Transmitter Channel PCS  ; 0                                             ;
; Total GXB Transmitter Channel PMA  ; 0                                             ;
; Total PLLs                         ; 0                                             ;
+------------------------------------+-----------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name                                                      ; mesi_isc           ; mesi_isc           ;
; Family name                                                                ; Cyclone IV GX      ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                            ;
+---------------------------------------+-----------------+------------------------+----------------------------------------------------------------------+---------+
; File Name with User-Entered Path      ; Used in Netlist ; File Type              ; File Name with Absolute Path                                         ; Library ;
+---------------------------------------+-----------------+------------------------+----------------------------------------------------------------------+---------+
; ../src/rtl/mesi_isc_define.v          ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_define.v          ;         ;
; ../src/rtl/mesi_isc_broad_cntl.v      ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v      ;         ;
; ../src/rtl/mesi_isc_broad.v           ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v           ;         ;
; ../src/rtl/mesi_isc_breq_fifos_cntl.v ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v ;         ;
; ../src/rtl/mesi_isc_breq_fifos.v      ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v      ;         ;
; ../src/rtl/mesi_isc_basic_fifo.v      ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v      ;         ;
; ../src/rtl/mesi_isc.v                 ; yes             ; User Verilog HDL File  ; /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v                 ;         ;
+---------------------------------------+-----------------+------------------------+----------------------------------------------------------------------+---------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; I/O pins             ; 194                  ;
; Maximum fan-out node ; clk~input            ;
; Maximum fan-out      ; 636                  ;
; Total fan-out        ; 4466                 ;
; Average fan-out      ; 2.97                 ;
+----------------------+----------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                    ;
+-----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                 ; Library Name ;
+-----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------+--------------+
; |mesi_isc                                                 ; 481 (0)           ; 636 (0)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 194  ; 0            ; |mesi_isc                                                                                           ;              ;
;    |mesi_isc_breq_fifos:mesi_isc_breq_fifos|              ; 312 (0)           ; 440 (0)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos                                                   ;              ;
;       |mesi_isc_basic_fifo:fifo_0|                        ; 41 (41)           ; 106 (106)    ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0                        ;              ;
;       |mesi_isc_basic_fifo:fifo_1|                        ; 41 (41)           ; 106 (106)    ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1                        ;              ;
;       |mesi_isc_basic_fifo:fifo_2|                        ; 41 (41)           ; 106 (106)    ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2                        ;              ;
;       |mesi_isc_basic_fifo:fifo_3|                        ; 41 (41)           ; 106 (106)    ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3                        ;              ;
;       |mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl| ; 148 (148)         ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl ;              ;
;    |mesi_isc_broad:mesi_isc_broad|                        ; 169 (0)           ; 196 (0)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_broad:mesi_isc_broad                                                             ;              ;
;       |mesi_isc_basic_fifo:broad_fifo|                    ; 124 (124)         ; 186 (186)    ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo                              ;              ;
;       |mesi_isc_broad_cntl:mesi_isc_broad_cntl|           ; 45 (45)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl                     ;              ;
+-----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 636   ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 136   ;
; Number of registers using Asynchronous Clear ; 636   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 427   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                          ;
+-------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                           ; Fan out ;
+-------------------------------------------------------------------------------------------------------------+---------+
; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifos_priority[0] ; 9       ;
; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|status_empty                             ; 39      ;
; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|status_empty                             ; 39      ;
; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|status_empty                             ; 39      ;
; mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|status_empty                             ; 39      ;
; mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|status_empty                                   ; 47      ;
; Total number of inverted registers = 6                                                                      ;         ;
+-------------------------------------------------------------------------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                      ;
+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered                                                                                                            ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+
; 5:1                ; 34 bits   ; 102 LEs       ; 68 LEs               ; 34 LEs                 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0|data_o[27]                               ;                            ;
; 5:1                ; 34 bits   ; 102 LEs       ; 68 LEs               ; 34 LEs                 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1|data_o[33]                               ;                            ;
; 5:1                ; 34 bits   ; 102 LEs       ; 68 LEs               ; 34 LEs                 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2|data_o[29]                               ;                            ;
; 5:1                ; 34 bits   ; 102 LEs       ; 68 LEs               ; 34 LEs                 ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3|data_o[25]                               ;                            ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_en_access_array[3]        ;                            ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl|cbus_active_broad_array[2]            ;                            ;
; 9:1                ; 36 bits   ; 216 LEs       ; 108 LEs              ; 108 LEs                ; |mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo|data_o[21]                                     ;                            ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; |mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl|fifo_select_oh[0] ;                            ;
+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+


+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |mesi_isc ;
+--------------------------+-------+---------------------------------------+
; Parameter Name           ; Value ; Type                                  ;
+--------------------------+-------+---------------------------------------+
; CBUS_CMD_WIDTH           ; 3     ; Signed Integer                        ;
; ADDR_WIDTH               ; 32    ; Signed Integer                        ;
; BROAD_TYPE_WIDTH         ; 2     ; Signed Integer                        ;
; BROAD_ID_WIDTH           ; 5     ; Signed Integer                        ;
; BROAD_REQ_FIFO_SIZE      ; 4     ; Signed Integer                        ;
; BROAD_REQ_FIFO_SIZE_LOG2 ; 2     ; Signed Integer                        ;
; MBUS_CMD_WIDTH           ; 3     ; Signed Integer                        ;
; BREQ_FIFO_SIZE           ; 2     ; Signed Integer                        ;
; BREQ_FIFO_SIZE_LOG2      ; 1     ; Signed Integer                        ;
+--------------------------+-------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad ;
+--------------------------+-------+-----------------------------------------+
; Parameter Name           ; Value ; Type                                    ;
+--------------------------+-------+-----------------------------------------+
; CBUS_CMD_WIDTH           ; 3     ; Signed Integer                          ;
; ADDR_WIDTH               ; 32    ; Signed Integer                          ;
; BROAD_TYPE_WIDTH         ; 2     ; Signed Integer                          ;
; BROAD_ID_WIDTH           ; 5     ; Signed Integer                          ;
; BROAD_REQ_FIFO_SIZE      ; 4     ; Signed Integer                          ;
; BROAD_REQ_FIFO_SIZE_LOG2 ; 2     ; Signed Integer                          ;
+--------------------------+-------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl ;
+------------------+-------+-----------------------------------------------------------------------------------------+
; Parameter Name   ; Value ; Type                                                                                    ;
+------------------+-------+-----------------------------------------------------------------------------------------+
; CBUS_CMD_WIDTH   ; 3     ; Signed Integer                                                                          ;
; BROAD_TYPE_WIDTH ; 2     ; Signed Integer                                                                          ;
; BROAD_ID_WIDTH   ; 5     ; Signed Integer                                                                          ;
+------------------+-------+-----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo ;
+----------------+-------+----------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                             ;
+----------------+-------+----------------------------------------------------------------------------------+
; DATA_WIDTH     ; 41    ; Signed Integer                                                                   ;
; FIFO_SIZE      ; 4     ; Signed Integer                                                                   ;
; FIFO_SIZE_LOG2 ; 2     ; Signed Integer                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos ;
+---------------------+-------+--------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                   ;
+---------------------+-------+--------------------------------------------------------+
; MBUS_CMD_WIDTH      ; 3     ; Signed Integer                                         ;
; ADDR_WIDTH          ; 32    ; Signed Integer                                         ;
; BROAD_TYPE_WIDTH    ; 2     ; Signed Integer                                         ;
; BROAD_ID_WIDTH      ; 5     ; Signed Integer                                         ;
; BREQ_FIFO_SIZE      ; 2     ; Signed Integer                                         ;
; BREQ_FIFO_SIZE_LOG2 ; 1     ; Signed Integer                                         ;
+---------------------+-------+--------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl ;
+------------------+-------+-------------------------------------------------------------------------------------------------------------+
; Parameter Name   ; Value ; Type                                                                                                        ;
+------------------+-------+-------------------------------------------------------------------------------------------------------------+
; MBUS_CMD_WIDTH   ; 3     ; Signed Integer                                                                                              ;
; ADDR_WIDTH       ; 32    ; Signed Integer                                                                                              ;
; BROAD_TYPE_WIDTH ; 2     ; Signed Integer                                                                                              ;
; BROAD_ID_WIDTH   ; 5     ; Signed Integer                                                                                              ;
+------------------+-------+-------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3 ;
+----------------+-------+----------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------+
; DATA_WIDTH     ; 41    ; Signed Integer                                                                         ;
; FIFO_SIZE      ; 2     ; Signed Integer                                                                         ;
; FIFO_SIZE_LOG2 ; 1     ; Signed Integer                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2 ;
+----------------+-------+----------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------+
; DATA_WIDTH     ; 41    ; Signed Integer                                                                         ;
; FIFO_SIZE      ; 2     ; Signed Integer                                                                         ;
; FIFO_SIZE_LOG2 ; 1     ; Signed Integer                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1 ;
+----------------+-------+----------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------+
; DATA_WIDTH     ; 41    ; Signed Integer                                                                         ;
; FIFO_SIZE      ; 2     ; Signed Integer                                                                         ;
; FIFO_SIZE_LOG2 ; 1     ; Signed Integer                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0 ;
+----------------+-------+----------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------+
; DATA_WIDTH     ; 41    ; Signed Integer                                                                         ;
; FIFO_SIZE      ; 2     ; Signed Integer                                                                         ;
; FIFO_SIZE_LOG2 ; 1     ; Signed Integer                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_0"                         ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                             ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; data_o[6..5] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_1"                         ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                             ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; data_o[6..5] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_2"                         ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                             ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; data_o[6..5] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"                         ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                             ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; data_o[6..5] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl"                                                                                            ;
+----------------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Port                       ; Type  ; Severity ; Details                                                                                                                                      ;
+----------------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; fifo_status_almost_empty_i ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; fifo_status_almost_full_i  ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
+----------------------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:02     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
    Info: Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition
    Info: Processing started: Tue Dec 25 13:54:09 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 0 design units, including 0 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_define.v
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v
    Info (12023): Found entity 1: mesi_isc_broad_cntl
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v
    Info (12023): Found entity 1: mesi_isc_broad
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v
    Info (12023): Found entity 1: mesi_isc_breq_fifos_cntl
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v
    Info (12023): Found entity 1: mesi_isc_breq_fifos
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v
    Info (12023): Found entity 1: mesi_isc_basic_fifo
Info (12021): Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v
    Info (12023): Found entity 1: mesi_isc
Info (12127): Elaborating entity "mesi_isc" for the top level hierarchy
Info (12128): Elaborating entity "mesi_isc_broad" for hierarchy "mesi_isc_broad:mesi_isc_broad"
Info (12128): Elaborating entity "mesi_isc_broad_cntl" for hierarchy "mesi_isc_broad:mesi_isc_broad|mesi_isc_broad_cntl:mesi_isc_broad_cntl"
Info (12128): Elaborating entity "mesi_isc_basic_fifo" for hierarchy "mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo"
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(122): truncated value with size 32 to match size of target (2)
Warning (10240): Verilog HDL Always Construct warning at mesi_isc_basic_fifo.v(112): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(154): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(157): truncated value with size 32 to match size of target (2)
Info (12128): Elaborating entity "mesi_isc_breq_fifos" for hierarchy "mesi_isc_breq_fifos:mesi_isc_breq_fifos"
Info (12128): Elaborating entity "mesi_isc_breq_fifos_cntl" for hierarchy "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl"
Warning (10230): Verilog HDL assignment warning at mesi_isc_breq_fifos_cntl.v(371): truncated value with size 32 to match size of target (3)
Info (12128): Elaborating entity "mesi_isc_basic_fifo" for hierarchy "mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(122): truncated value with size 32 to match size of target (1)
Warning (10240): Verilog HDL Always Construct warning at mesi_isc_basic_fifo.v(112): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(154): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at mesi_isc_basic_fifo.v(157): truncated value with size 32 to match size of target (1)
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info (286030): Timing-Driven Synthesis is running
Info (144001): Generated suppressed messages file /home/yair/Work/Projects/mesi_isc/syn/mesi_isc.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 1101 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 146 input pins
    Info (21059): Implemented 48 output pins
    Info (21061): Implemented 907 logic cells
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Peak virtual memory: 370 megabytes
    Info: Processing ended: Tue Dec 25 13:54:13 2012
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:04


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /home/yair/Work/Projects/mesi_isc/syn/mesi_isc.map.smsg.


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