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PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/ PROJECT_SRC=altera_virtual_jtag.vhd
PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/
PROJECT_SRC=altera_virtual_jtag.vhd
