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PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog PROJECT_SRC=(tap_top.v tap_defines.v)
PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
PROJECT_SRC=(tap_top.v
tap_defines.v)