URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
[/] [mod_sim_exp/] [trunk/] [syn/] [xilinx/] [log/] [fifo/] [generic_fifo_dc_gray_aw7_summary.html] - Rev 94
Compare with Previous | Blame | View Log
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='4'><B>mod_sim_exp_core Project Status (07/03/2013 - 16:32:22)</B></TD></TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD>msec.xise</TD> <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> <TD> No Errors </TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> <TD>generic_fifo_dc_gray</TD> <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> <TD>Synthesized</TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> <TD>xc6vlx240t-1ff1156</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> <TD> No Errors</TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.4</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> <TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/*.xmsgs?&DataKey=Warning'>20 Warnings (8 new)</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> <TD>Balanced</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> <TD> </TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> <TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> <TD> </TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> <TD> <A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray_envsettings.html'> System Settings</A> </TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> <TD> </TD> </TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#FFFF99'> <TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> <TD ALIGN=RIGHT>78</TD> <TD ALIGN=RIGHT>301440</TD> <TD ALIGN=RIGHT COLSPAN='2'>0%</TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> <TD ALIGN=RIGHT>95</TD> <TD ALIGN=RIGHT>150720</TD> <TD ALIGN=RIGHT COLSPAN='2'>0%</TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD> <TD ALIGN=RIGHT>67</TD> <TD ALIGN=RIGHT>106</TD> <TD ALIGN=RIGHT COLSPAN='2'>63%</TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>600</TD> <TD ALIGN=RIGHT COLSPAN='2'>0%</TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD> <TD ALIGN=RIGHT>1</TD> <TD ALIGN=RIGHT>416</TD> <TD ALIGN=RIGHT COLSPAN='2'>0%</TD> </TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jul 3 16:32:21 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Warning'>20 Warnings (8 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Info'>4 Infos (2 new)</A></TD></TR> <TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> </TABLE> <br><center><b>Date Generated:</b> 07/03/2013 - 16:32:22</center> </BODY></HTML>