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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD><TITLE>Synthesis Report</TITLE> <META content="text/html; charset=windows-1252" http-equiv=Content-Type> <META name=GENERATOR content="MSHTML 9.00.8112.16457"></HEAD> <BODY><PRE><FONT&NBSP;FACE="COURIER&NBSP;NEW",&NBSP;MONOTYPE><P&NBSP;ALIGN=LEFT><B>Synthesis Report</B><P></P><B><CENTER>wo 6. mrt 15:12:33 2013</CENTER></B><BR><HR><BR>Release 12.4 - xst M.81d (nt)<BR>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.<BR>--> Parameter TMPDIR set to xst/projnav.tmp<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.12 secs<BR> <BR>--> Parameter xsthdpdir set to xst<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.13 secs<BR> <BR>--> Reading design: fifo_primitive.prj<BR><BR>TABLE OF CONTENTS<BR> 1) Synthesis Options Summary<BR> 2) HDL Parsing<BR> 3) HDL Elaboration<BR> 4) HDL Synthesis<BR> 4.1) HDL Synthesis Report<BR> 5) Advanced HDL Synthesis<BR> 5.1) Advanced HDL Synthesis Report<BR> 6) Low Level Synthesis<BR> 7) Partition Report<BR> 8) Design Summary<BR> 8.1) Primitive and Black Box Usage<BR> 8.2) Device utilization summary<BR> 8.3) Partition Resource Summary<BR> 8.4) Timing Report<BR> 8.4.1) Clock Information<BR> 8.4.2) Asynchronous Control Signals Information<BR> 8.4.3) Timing Summary<BR> 8.4.4) Timing Details<BR> 8.4.5) Cross Clock Domains Report<BR><BR><BR>=========================================================================<BR>* Synthesis Options Summary *<BR>=========================================================================<BR>---- Source Parameters<BR>Input File Name : "fifo_primitive.prj"<BR>Input Format : mixed<BR>Ignore Synthesis Constraint File : NO<BR><BR>---- Target Parameters<BR>Output File Name : "fifo_primitive"<BR>Output Format : NGC<BR>Target Device : xc6vlx240t-1-ff1156<BR><BR>---- Source Options<BR>Top Module Name : fifo_primitive<BR>Automatic FSM Extraction : YES<BR>FSM Encoding Algorithm : Auto<BR>Safe Implementation : No<BR>FSM Style : LUT<BR>RAM Extraction : Yes<BR>RAM Style : Auto<BR>ROM Extraction : Yes<BR>Shift Register Extraction : YES<BR>ROM Style : Auto<BR>Resource Sharing : YES<BR>Asynchronous To Synchronous : NO<BR>Shift Register Minimum Size : 2<BR>Use DSP Block : Auto<BR>Automatic Register Balancing : No<BR><BR>---- Target Options<BR>LUT Combining : Auto<BR>Reduce Control Sets : Auto<BR>Add IO Buffers : NO<BR>Global Maximum Fanout : 100000<BR>Add Generic Clock Buffer(BUFG) : 32<BR>Register Duplication : YES<BR>Optimize Instantiated Primitives : NO<BR>Use Clock Enable : Auto<BR>Use Synchronous Set : Auto<BR>Use Synchronous Reset : Auto<BR>Pack IO Registers into IOBs : Auto<BR>Equivalent register Removal : YES<BR><BR>---- General Options<BR>Optimization Goal : Area<BR>Optimization Effort : 2<BR>Power Reduction : NO<BR>Keep Hierarchy : No<BR>Netlist Hierarchy : As_Optimized<BR>RTL Output : Yes<BR>Global Optimization : AllClockNets<BR>Read Cores : YES<BR>Write Timing Constraints : NO<BR>Cross Clock Analysis : NO<BR>Hierarchy Separator : /<BR>Bus Delimiter : <><BR>Case Specifier : Maintain<BR>Slice Utilization Ratio : 100<BR>BRAM Utilization Ratio : 100<BR>DSP48 Utilization Ratio : 100<BR>Auto BRAM Packing : NO<BR>Slice Utilization Ratio Delta : 5<BR><BR>---- Other Options<BR>Cores Search Directories : {"../../SVN/mod_sim_exp/rtl/vhdl/core" }<BR><BR>=========================================================================<BR><BR><BR>=========================================================================<BR>* HDL Parsing *<BR>=========================================================================<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/fifo_primitive.vhd" into library mod_sim_exp<BR>Parsing entity <FIFO_PRIMITIVE>.<BR>Parsing architecture <BEHAVIORAL> of entity <FIFO_PRIMITIVE>.<BR><BR>=========================================================================<BR>* HDL Elaboration *<BR>=========================================================================<BR><BR>Elaborating entity <FIFO_PRIMITIVE> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>=========================================================================<BR>* HDL Synthesis *<BR>=========================================================================<BR><BR>Synthesizing Unit <FIFO_PRIMITIVE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/fifo_primitive.vhd".<BR> Found 1-bit register for signal <RESET_I>.<BR> Found 2-bit register for signal <RESET_PROC.CLK_COUNTER>.<BR> Found 2-bit subtractor for signal <GND_6_O_GND_6_O_SUB_2_OUT<1:0>> created at line 100.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 3 D-type flip-flop(s).<BR> inferred 1 Multiplexer(s).<BR>Unit <FIFO_PRIMITIVE> synthesized.<BR><BR>=========================================================================<BR>HDL Synthesis Report<BR><BR>Macro Statistics<BR># Adders/Subtractors : 1<BR> 2-bit subtractor : 1<BR># Registers : 2<BR> 1-bit register : 1<BR> 2-bit register : 1<BR># Multiplexers : 1<BR> 2-bit 2-to-1 multiplexer : 1<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Advanced HDL Synthesis *<BR>=========================================================================<BR><BR><BR>=========================================================================<BR>Advanced HDL Synthesis Report<BR><BR>Macro Statistics<BR># Adders/Subtractors : 1<BR> 2-bit subtractor : 1<BR># Registers : 3<BR> Flip-Flops : 3<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Low Level Synthesis *<BR>=========================================================================<BR><BR>Optimizing unit <FIFO_PRIMITIVE> ...<BR><BR>Mapping all equations...<BR>Building and optimizing final netlist ...<BR>Found area constraint ratio of 100 (+ 5) on block fifo_primitive, actual ratio is 0.<BR><BR>Final Macro Processing ...<BR><BR>=========================================================================<BR>Final Register Report<BR><BR>Macro Statistics<BR># Registers : 3<BR> Flip-Flops : 3<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Partition Report *<BR>=========================================================================<BR><BR>Partition Implementation Status<BR>-------------------------------<BR><BR> No Partitions were found in this design.<BR><BR>-------------------------------<BR><BR>=========================================================================<BR>* Design Summary *<BR>=========================================================================<BR><BR>Top Level Output File Name : fifo_primitive.ngc<BR><BR>Primitive and Black Box Usage:<BR>------------------------------<BR># BELS : 9<BR># GND : 1<BR># LUT2 : 5<BR># LUT3 : 2<BR># VCC : 1<BR># FlipFlops/Latches : 3<BR># FDP : 3<BR># RAMS : 1<BR># FIFO18E1 : 1<BR><BR>Device utilization summary:<BR>---------------------------<BR><BR>Selected Device : 6vlx240tff1156-1 <BR><BR><BR>Slice Logic Utilization: <BR> Number of Slice Registers: 3 out of 301440 0% <BR> Number of Slice LUTs: 7 out of 150720 0% <BR> Number used as Logic: 7 out of 150720 0% <BR><BR>Slice Logic Distribution: <BR> Number of LUT Flip Flop pairs used: 10<BR> Number with an unused Flip Flop: 7 out of 10 70% <BR> Number with an unused LUT: 3 out of 10 30% <BR> Number of fully used LUT-FF pairs: 0 out of 10 0% <BR> Number of unique control sets: 1<BR><BR>IO Utilization: <BR> Number of IOs: 72<BR> Number of bonded IOBs: 0 out of 600 0% <BR><BR>Specific Feature Utilization:<BR> Number of Block RAM/FIFO: 1 out of 416 0% <BR> Number using FIFO only: 1<BR><BR>---------------------------<BR>Partition Resource Summary:<BR>---------------------------<BR><BR> No Partitions were found in this design.<BR><BR>---------------------------<BR><BR><BR>=========================================================================<BR>Timing Report<BR><BR>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<BR> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<BR> GENERATED AFTER PLACE-and-ROUTE.<BR><BR>Clock Information:<BR>------------------<BR>-----------------------------------+------------------------+-------+<BR>Clock Signal | Clock buffer(FF name) | Load |<BR>-----------------------------------+------------------------+-------+<BR>clk | NONE(reset_i) | 4 |<BR>-----------------------------------+------------------------+-------+<BR>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<BR><BR>Asynchronous Control Signals Information:<BR>----------------------------------------<BR>No asynchronous control signals found in this design<BR><BR>Timing Summary:<BR>---------------<BR>Speed Grade: -1<BR><BR> Minimum period: 1.842ns (Maximum Frequency: 542.888MHz)<BR> Minimum input arrival time before clock: 1.109ns<BR> Maximum output required time after clock: 2.145ns<BR> Maximum combinational path delay: 0.250ns<BR><BR>Timing Details:<BR>---------------<BR>All values displayed in nanoseconds (ns)<BR><BR>=========================================================================<BR>Timing constraint: Default period analysis for Clock 'clk'<BR> Clock period: 1.842ns (frequency: 542.888MHz)<BR> Total number of paths / destination ports: 9 / 6<BR>-------------------------------------------------------------------------<BR>Delay: 1.842ns (Levels of Logic = 1)<BR> Source: reset_i (FF)<BR> Destination: FIFO18E1_inst (UNKNOWN)<BR> Source Clock: clk rising<BR> Destination Clock: clk rising<BR><BR> Data Path: reset_i to FIFO18E1_inst<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> FDP:C->Q 6 0.375 0.450 reset_i (reset_i)<BR> LUT2:I1->O 1 0.068 0.399 push_i1 (push_i)<BR> FIFO18E1:WREN 0.550 FIFO18E1_inst<BR> ----------------------------------------<BR> Total 1.842ns (0.993ns logic, 0.849ns route)<BR> (53.9% logic, 46.1% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'<BR> Total number of paths / destination ports: 5 / 5<BR>-------------------------------------------------------------------------<BR>Offset: 1.109ns (Levels of Logic = 1)<BR> Source: push (PAD)<BR> Destination: FIFO18E1_inst (UNKNOWN)<BR> Destination Clock: clk rising<BR><BR> Data Path: push to FIFO18E1_inst<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT2:I0->O 1 0.068 0.399 push_i1 (push_i)<BR> FIFO18E1:WREN 0.550 FIFO18E1_inst<BR> ----------------------------------------<BR> Total 1.109ns (0.710ns logic, 0.399ns route)<BR> (64.0% logic, 36.0% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'<BR> Total number of paths / destination ports: 42 / 36<BR>-------------------------------------------------------------------------<BR>Offset: 2.145ns (Levels of Logic = 2)<BR> Source: reset_i (FF)<BR> Destination: nopush (PAD)<BR> Source Clock: clk rising<BR><BR> Data Path: reset_i to nopush<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> FDP:C->Q 6 0.375 0.432 reset_i (reset_i)<BR> FIFO18E1:RST->WRERR 1 0.853 0.417 FIFO18E1_inst (wrerr_i)<BR> LUT3:I2->O 0 0.068 0.000 nopush1 (nopush)<BR> ----------------------------------------<BR> Total 2.145ns (1.296ns logic, 0.849ns route)<BR> (60.4% logic, 39.6% route)<BR><BR>=========================================================================<BR>Timing constraint: Default path analysis<BR> Total number of paths / destination ports: 2 / 2<BR>-------------------------------------------------------------------------<BR>Delay: 0.250ns (Levels of Logic = 1)<BR> Source: pop (PAD)<BR> Destination: nopop (PAD)<BR><BR> Data Path: pop to nopop<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT3:I0->O 0 0.068 0.000 nopop1 (nopop)<BR> ----------------------------------------<BR> Total 0.250ns (0.250ns logic, 0.000ns route)<BR> (100.0% logic, 0.0% route)<BR><BR>=========================================================================<BR><BR>Cross Clock Domains Report:<BR>--------------------------<BR><BR>Clock to Setup on destination clock clk<BR>---------------+---------+---------+---------+---------+<BR> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<BR>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<BR>---------------+---------+---------+---------+---------+<BR>clk | 1.842| | | |<BR>---------------+---------+---------+---------+---------+<BR><BR>=========================================================================<BR><BR><BR>Total REAL time to Xst completion: 4.00 secs<BR>Total CPU time to Xst completion: 3.94 secs<BR> <BR>--> <BR><BR>Total memory usage is 239608 kilobytes<BR><BR>Number of errors : 0 ( 0 filtered)<BR>Number of warnings : 0 ( 0 filtered)<BR>Number of infos : 1 ( 0 filtered)<BR><BR></PRE></FONT></BODY></HTML>