--dffpipe DELAY=2 WIDTH=5 clock d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 15.1 cbx_mgl 2015:10:21:18:12:49:SJ cbx_stratixii 2015:10:21:18:09:23:SJ cbx_util_mgl 2015:10:21:18:09:23:SJ  VERSION_END


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--synthesis_resources = reg 10 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_3v8
( 
	clock	:	input;
	d[4..0]	:	input;
	q[4..0]	:	output;
) 
VARIABLE 
	dffe10a[4..0] : dffe;
	dffe11a[4..0] : dffe;
	clrn	: NODE;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe10a[].clk = clock;
	dffe10a[].clrn = clrn;
	dffe10a[].d = (d[] & (! sclr));
	dffe10a[].ena = ena;
	dffe10a[].prn = prn;
	dffe11a[].clk = clock;
	dffe11a[].clrn = clrn;
	dffe11a[].d = (dffe10a[].q & (! sclr));
	dffe11a[].ena = ena;
	dffe11a[].prn = prn;
	clrn = VCC;
	ena = VCC;
	prn = VCC;
	q[] = dffe11a[].q;
	sclr = GND;
END;
--VALID FILE
