
//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

module Next186_SoC(

//////////// CLOCK //////////
	input CLOCK_50,
//input CLOCK2_50,
//input CLOCK3_50,

//////////// LED //////////
	output [8:0]LEDG,
	output [17:0]LEDR,

//////////// KEY //////////
	input [3:0]KEY,

//////////// RS232 //////////
//input UART_CTS,
//output UART_RTS,
	input UART_RXD,
	output UART_TXD,

//////////// PS2 for Keyboard and Mouse //////////
	inout PS2_CLK,
	inout PS2_CLK2,
	inout PS2_DAT,
	inout PS2_DAT2,

//////////// SDCARD //////////
	output SD_CLK,
	inout  SD_CMD,
	inout [3:0]SD_DAT,
	input SD_WP_N,

//////////// VGA //////////
	output [7:0]VGA_B,
	output VGA_BLANK_N,
	output VGA_CLK,
	output [7:0]VGA_G,
	output VGA_HS,
	output [7:0]VGA_R,
	output VGA_SYNC_N,
	output VGA_VS,

//////////// Audio //////////
	input  AUD_ADCDAT,
	inout  AUD_ADCLRCK,
	inout  AUD_BCLK,
	output AUD_DACDAT,
	inout  AUD_DACLRCK,
	output AUD_XCK,

//////////// I2C for Audio  //////////
	output I2C_SCLK,
	inout  I2C_SDAT,

//////////// SDRAM //////////
	output [12:0]DRAM_ADDR,
	output  [1:0]DRAM_BA,
	output  DRAM_CAS_N,
	output  DRAM_CKE,
	output  DRAM_CLK,
	output  DRAM_CS_N,
	inout  [31:0]DRAM_DQ,
	output  [3:0]DRAM_DQM,
	output  DRAM_RAS_N,
	output  DRAM_WE_N,

//////////// GPIO //////////
	inout	[35:0]GPIO
);

	wire CLK44100x256;
	wire [31:0]snd_sample;
	reg [31:0]sndsend;

	assign DRAM_CKE = 1'b1;
	assign VGA_R[1:0] = 2'b00;
	assign VGA_G[1:0] = 2'b00;
	assign VGA_B[1:0] = 2'b00;
	assign VGA_SYNC_N = ~(VGA_HS | VGA_VS);
	assign DRAM_DQM[3:2] = DRAM_DQM[1:0];
	assign LEDG[8] = 1'b0;
	assign LEDR = 0;
	assign AUD_DACDAT = sndsend[31];
 
	
	wire SDR_CLK;
	dd_buf sdrclk_buf
	(
		.datain_h(1'b1),
		.datain_l(1'b0),
		.outclock(SDR_CLK),
		.dataout(DRAM_CLK)
	);

	wire clk_25;
	dd_buf vgaclk_buf
	(
		.datain_h(1'b1),
		.datain_l(1'b0),
		.outclock(clk_25),
		.dataout(VGA_CLK)
	);

	dd_buf XCKclk_buf
	(
		.datain_h(1'b1),
		.datain_l(1'b0),
		.outclock(CLK44100x256),
		.dataout(AUD_XCK)
	);

	dd_buf BCLKclk_buf
	(
		.datain_h(1'b1),
		.datain_l(1'b0),
		.outclock(CLK44100x256),
		.dataout(AUD_BCLK)
	);
	
	system sys_inst
	(
		.CLK_50MHZ(CLOCK_50),
		.VGA_R(VGA_R[7:2]),
		.VGA_G(VGA_G[7:2]),
		.VGA_B(VGA_B[7:2]),
		.frame_on(VGA_BLANK_N),
		.VGA_HSYNC(VGA_HS),
		.VGA_VSYNC(VGA_VS),
		.clk_25(clk_25),
		.sdr_CLK_out(SDR_CLK),
		.sdr_n_CS_WE_RAS_CAS({DRAM_CS_N, DRAM_WE_N, DRAM_RAS_N, DRAM_CAS_N}),
		.sdr_BA(DRAM_BA),
		.sdr_ADDR(DRAM_ADDR),
		.sdr_DATA(DRAM_DQ),
		.sdr_DQM({DRAM_DQM[1:0]}),
		.LED(LEDG[7:0]),
		.BTN_RESET(~KEY[0]),
		.BTN_NMI(~KEY[1]),
		.RS232_DCE_RXD(UART_RXD),
		.RS232_DCE_TXD(UART_TXD),
		.RS232_EXT_RXD(GPIO[8]),
		.RS232_EXT_TXD(GPIO[9]),
		.SD_n_CS(SD_DAT[3]),
		.SD_DI(SD_CMD),
		.SD_CK(SD_CLK),
		.SD_DO(SD_DAT[0]),
		.AUD_L(GPIO[10]),
		.AUD_R(GPIO[11]),
	 	.PS2_CLK1(PS2_CLK),
		.PS2_CLK2(PS2_CLK2),
		.PS2_DATA1(PS2_DAT),
		.PS2_DATA2(PS2_DAT2),
		.RS232_HOST_RXD(),
		.RS232_HOST_TXD(),
		.RS232_HOST_RST(),
		.GPIO(GPIO[7:0]),
		.I2C_SCL(I2C_SCLK),
		.I2C_SDA(I2C_SDAT),
		.CLK44100x256(CLK44100x256),
		.snd_sample(snd_sample), // L,R
		.sample_rdy(AUD_DACLRCK)
	);

	
	always @(posedge CLK44100x256)
		if(AUD_DACLRCK) sndsend <= snd_sample ^ 32'h80008000; // L,R - convert to signed 2C
		else sndsend <= sndsend << 1;

	
endmodule

