--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_REG_B="CLOCK1" INIT_FILE="font.mif" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 NUMWORDS_B=256 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=32 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=10 WIDTHAD_B=8 WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 14.0 cbx_altsyncram 2014:06:17:18:06:03:SJ cbx_cycloneii 2014:06:17:18:06:03:SJ cbx_lpm_add_sub 2014:06:17:18:06:03:SJ cbx_lpm_compare 2014:06:17:18:06:03:SJ cbx_lpm_decode 2014:06:17:18:06:03:SJ cbx_lpm_mux 2014:06:17:18:06:03:SJ cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratix 2014:06:17:18:06:03:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_stratixiii 2014:06:17:18:06:03:SJ cbx_stratixv 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
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--  Subscription Agreement, the Altera Quartus II License Agreement,
--  the Altera MegaCore Function License Agreement, or other 
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--  that your use is for the sole purpose of programming logic 
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--  authorized distributors.  Please refer to the applicable 
--  agreement for further details.


FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = M9K 2 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_2qh2
( 
	address_a[9..0]	:	input;
	address_b[7..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	data_a[7..0]	:	input;
	data_b[31..0]	:	input;
	q_a[7..0]	:	output;
	q_b[31..0]	:	output;
	wren_a	:	input;
	wren_b	:	input;
) 
VARIABLE 
	ram_block1a0 : cycloneive_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "none",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 8,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "font.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 4,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a1 : cycloneive_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "none",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 8,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "font.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 4,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a2 : cycloneive_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "none",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 8,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "font.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 4,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a3 : cycloneive_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "none",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 8,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "font.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 4,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 3,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a4 : cycloneive_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "none",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 8,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "font.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 4,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a5 : cycloneive_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "none",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 8,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "font.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 4,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a6 : cycloneive_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "none",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 8,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "font.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 4,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a7 : cycloneive_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "none",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			DATA_INTERLEAVE_OFFSET_IN_BITS = 8,
			DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
			INIT_FILE = "font.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 10,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 1023,
			PORT_A_LOGICAL_RAM_DEPTH = 1024,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 4,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			PORT_B_WRITE_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	address_a_wire[9..0]	: WIRE;
	address_b_wire[7..0]	: WIRE;

BEGIN 
	ram_block1a[7..0].clk0 = clock0;
	ram_block1a[7..0].clk1 = clock1;
	ram_block1a[7..0].portaaddr[] = ( address_a_wire[9..0]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[1..1]);
	ram_block1a[2].portadatain[] = ( data_a[2..2]);
	ram_block1a[3].portadatain[] = ( data_a[3..3]);
	ram_block1a[4].portadatain[] = ( data_a[4..4]);
	ram_block1a[5].portadatain[] = ( data_a[5..5]);
	ram_block1a[6].portadatain[] = ( data_a[6..6]);
	ram_block1a[7].portadatain[] = ( data_a[7..7]);
	ram_block1a[7..0].portare = B"11111111";
	ram_block1a[7..0].portawe = wren_a;
	ram_block1a[7..0].portbaddr[] = ( address_b_wire[7..0]);
	ram_block1a[0].portbdatain[] = ( data_b[24..24], data_b[16..16], data_b[8..8], data_b[0..0]);
	ram_block1a[1].portbdatain[] = ( data_b[25..25], data_b[17..17], data_b[9..9], data_b[1..1]);
	ram_block1a[2].portbdatain[] = ( data_b[26..26], data_b[18..18], data_b[10..10], data_b[2..2]);
	ram_block1a[3].portbdatain[] = ( data_b[27..27], data_b[19..19], data_b[11..11], data_b[3..3]);
	ram_block1a[4].portbdatain[] = ( data_b[28..28], data_b[20..20], data_b[12..12], data_b[4..4]);
	ram_block1a[5].portbdatain[] = ( data_b[29..29], data_b[21..21], data_b[13..13], data_b[5..5]);
	ram_block1a[6].portbdatain[] = ( data_b[30..30], data_b[22..22], data_b[14..14], data_b[6..6]);
	ram_block1a[7].portbdatain[] = ( data_b[31..31], data_b[23..23], data_b[15..15], data_b[7..7]);
	ram_block1a[7..0].portbre = B"11111111";
	ram_block1a[7..0].portbwe = wren_b;
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_a[] = ( ram_block1a[7..0].portadataout[0..0]);
	q_b[] = ( ram_block1a[7..0].portbdataout[3..3], ram_block1a[7..0].portbdataout[2..2], ram_block1a[7..0].portbdataout[1..1], ram_block1a[7..0].portbdataout[0..0]);
END;
--VALID FILE
