/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.9.1.119 */
/* Module Version: 7.5 */
/* Tue Sep 19 16:10:02 2017 */

/* parameterized module instance */
DAC_SRAM __ (.DataInA( ), .DataInB( ), .AddressA( ), .AddressB( ), 
    .ClockA( ), .ClockB( ), .ClockEnA( ), .ClockEnB( ), .WrA( ), .WrB( ), 
    .ResetA( ), .ResetB( ), .QA( ), .QB( ));
