/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.9.1.119 */
/* Module Version: 5.8 */
/* Tue Sep 19 15:59:08 2017 */

/* parameterized module instance */
ioip __ (.clkout( ), .refclk( ), .reset( ), .data( ), .dout( ));
