SCUBA, Version Diamond (64-bit) 3.9.1.119
Fri Sep 15 13:57:24 2017
  
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
  
BEGIN SCUBA Module Synthesis
  
    Issued command   : C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n dcm -lang verilog -synth synplify -arch xo2c00 -type pll -fin 50 -fclkop 25 -fclkop_tol 0.1 -fclkos 100 -fclkos_tol 5.0 -fclkos2 100 -fclkos2_tol 5.0 -fclkos3 50 -fclkos3_tol 1.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phases2 225 -phases3 0 -phase_cntl STATIC -fb_mode 1 
    Circuit name     : dcm
    Module type      : pll
    Module Version   : 5.7
    Ports            : 
    Inputs       : CLKI
    Outputs      : CLKOP, CLKOS, CLKOS2, CLKOS3
    I/O buffer       : not inserted
    EDIF output      : dcm.edn
    Verilog output   : dcm.v
    Verilog template : dcm_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : dcm.srp
    Estimated Resource Usage:
  
END   SCUBA Module Synthesis

