SCUBA, Version Diamond (64-bit) 3.9.1.119
Tue Sep 19 16:10:02 2017

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n DAC_SRAM -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type ramdp -device LFE5U-25F -aaddr_width 10 -widtha 8 -baddr_width 8 -widthb 32 -anum_words 1024 -bnum_words 256 -cascade -1 -mem_init0 -writemodeA NORMAL -writemodeB NORMAL -fdc E:/Work/Lattice/Ohm/Next186_SoC/DAC_SRAM/DAC_SRAM.fdc 
    Circuit name     : DAC_SRAM
    Module type      : RAM_DP_TRUE
    Module Version   : 7.5
    Ports            : 
	Inputs       : DataInA[7:0], DataInB[31:0], AddressA[9:0], AddressB[7:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
	Outputs      : QA[7:0], QB[31:0]
    I/O buffer       : not inserted
    Memory file      : INIT_ALL_0s
    EDIF output      : DAC_SRAM.edn
    Verilog output   : DAC_SRAM.v
    Verilog template : DAC_SRAM_tmpl.v
    Verilog testbench: tb_DAC_SRAM_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : DAC_SRAM.srp
    Element Usage    :
         DP16KD : 2
    Estimated Resource Usage:
            EBR : 2
