/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.9.1.119 */
/* Module Version: 7.5 */
/* Thu Sep 21 09:44:04 2017 */

/* parameterized module instance */
cache __ (.DataInA( ), .DataInB( ), .ByteEnA( ), .ByteEnB( ), 
    .AddressA( ), .AddressB( ), .ClockA( ), .ClockB( ), .ClockEnA( ), 
    .ClockEnB( ), .WrA( ), .WrB( ), .ResetA( ), .ResetB( ), .QA( ), 
    .QB( ));
