/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.9.1.119 */
/* Module Version: 6.5 */
/* Wed Sep 20 10:51:50 2017 */

/* parameterized module instance */
datamem16 __ (.WrAddress( ), .RdAddress( ), .Data( ), .WE( ), 
    .RdClock( ), .RdClockEn( ), .Reset( ), .WrClock( ), .WrClockEn( ), 
    .Q( ));
