module FleaFPGA_2v4(
//    -- System clock and reset
	input sys_clock, // main clock input from external clock source
	input sys_reset, // main clock input from external RC reset circuit

//    -- On-board user buttons and status LEDs
	output n_led1,

//    -- User GPIO (18 I/O pins) Header
	inout [27:2]GPIO,  // GPIO Header pins available as one data block
	inout GPIO_IDSD,
	inout GPIO_IDSC,
	
	output [3:0]AD_EOUT,
	input [3:0]AD_FB,

//    -- USB Slave (FT230x) interface 
	output slave_tx_o,
	input slave_rx_i,
	 
//	-- SDRAM interface (For use with 16Mx16bit or 32Mx16bit SDR DRAM, depending on version)
	output Dram_Clk,	// clock to SDRAM
	output Dram_CKE,	// clock to SDRAM	
	output Dram_n_Ras,  // SDRAM RAS
	output Dram_n_Cas,	// SDRAM CAS
	output Dram_n_We,	// SDRAM write-enable
	output [1:0]Dram_BA,	// SDRAM bank-address
	output [12:0]Dram_Addr,	// SDRAM address bus
	inout [15:0]Dram_Data,	// data bus to/from SDRAM	
	output Dram_n_cs, 
	output Dram_DQMH,
	output Dram_DQML,
	  
//	-- DVI interface
	output [0:0]LVDS_Red,
	output [0:0]LVDS_Green,
	output [0:0]LVDS_Blue,
	output [0:0]LVDS_ck,
	
	 
//	-- SD/MMC Interface (Support either SPI or nibble-mode)
	input mmc_dat1,
	input mmc_dat2,
	output mmc_n_cs,
	output mmc_clk,
	output mmc_mosi,
	input mmc_miso,

//	-- PS2 interface (Both ports accessible via Y-splitter cable)
	output PS2_enable1,
	inout PS2_clk1,
	inout PS2_data1,
	inout PS2_clk2,
	inout PS2_data2 
    );
	
	assign Dram_CKE = 1'b1; 	// -- DRAM clock enable
	assign PS2_enable1 = 1'b0; 	// pull both USB ports D+ and D- to GND through 15K resistors
	wire [3:0]LED;
	assign n_led1 = LED[1];

	system sys_inst
	(
		.CLK_IN(sys_clock),
		.TMDS({LVDS_ck, LVDS_Red, LVDS_Green, LVDS_Blue}),
		.sdr_CLK_out(Dram_Clk),
		.sdr_n_CS_WE_RAS_CAS({Dram_n_cs, Dram_n_We, Dram_n_Ras, Dram_n_Cas}),
		.sdr_BA(Dram_BA),
		.sdr_ADDR(Dram_Addr),
		.sdr_DATA(Dram_Data),
		.sdr_DQM({Dram_DQMH, Dram_DQML}),
		.LED(LED),
		.BTN_RESET(!sys_reset),
		.BTN_NMI(!GPIO[2]),		// PIN3
		.RS232_DCE_RXD(slave_rx_i),
		.RS232_DCE_TXD(slave_tx_o),
		.SD_n_CS(mmc_n_cs),
		.SD_DI(mmc_mosi),
		.SD_CK(mmc_clk),
		.SD_DO(mmc_miso),
		.AUD_L(GPIO[3]),	// PIN5
		.AUD_R(GPIO[4]),	// PIN7
		.USB0_DM(PS2_data2), 
		.USB0_DP(PS2_clk2),
		.USB1_DM(PS2_data1), 
		.USB1_DP(PS2_clk1),
		.RS232_HOST_RXD(),
		.RS232_HOST_TXD(),
		.RS232_HOST_RST(),
		.RS232_EXT_RXD(GPIO[17]), // PIN11
		.RS232_EXT_TXD(GPIO[27]), // PIN13
		.GPIO({GPIO[7], GPIO[8], GPIO[25], GPIO[24], GPIO[23], GPIO[18], GPIO[15], GPIO[14]}) // PINS{26, 24, 22, 18, 16, 12, 10, 8}
	);

   
endmodule
