Starting process: 

Configuration data saved


SCUBA, Version Diamond (64-bit) 3.9.1.119
Tue Sep 19 16:13:22 2017

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.

BEGIN SCUBA Module Synthesis

    Issued command   : C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n sndfifo -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type ebfifo -depth 2048 -width 32 -rwidth 32 -reset_rel SYNC -pe 90 -pf 892 
    Circuit name     : sndfifo
    Module type      : ebfifo
    Module Version   : 5.8
    Ports            : 
	Inputs       : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
	Outputs      : Q[31:0], Empty, Full, AlmostEmpty, AlmostFull
    I/O buffer       : not inserted
    EDIF output      : sndfifo.edn
    Verilog output   : sndfifo.v
    Verilog template : sndfifo_tmpl.v
    Verilog testbench: tb_sndfifo_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : sndfifo.srp
    Estimated Resource Usage:
            LUT : 181
            EBR : 4
            Reg : 148

END   SCUBA Module Synthesis

File: sndfifo.lpc created.


End process: completed successfully.


Total Warnings:  0

Total Errors:  0


