/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.10.2.115 */
/* Module Version: 5.7 */
/* C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n dcm1 -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 25.00 -fclkop 48 -fclkop_tol 5.0 -phasep 0 -fclkos 29.4912 -fclkos_tol 2.0 -phases 0 -fclkos2 11.2896 -fclkos2_tol 1.0 -phases2 0 -fclkos3 90.00 -fclkos3_tol 2.0 -phase_cntl STATIC -fb_mode 4 -bw HIGH -fdc E:/Work/Lattice/Ohm/Next186_SoC/dcm1/dcm1.fdc  */
/* Tue Mar 12 16:27:32 2019 */


`timescale 1 ns / 1 ps
module dcm1 (CLKI, CLKOP, CLKOS, CLKOS2, CLKOS3)/* synthesis NGD_DRC_MASK=1 */;
    input wire CLKI;
    output wire CLKOP;
    output wire CLKOS;
    output wire CLKOS2;
    output wire CLKOS3;

    wire REFCLK;
    wire LOCK;
    wire CLKOS2_t;
    wire CLKOS_t;
    wire CLKOP_t;
    wire CLKOS3_t;
    wire scuba_vhi;
    wire scuba_vlo;

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
    defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
    defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
    defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
    defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
    defparam PLLInst_0.CLKOS3_CPHASE = 6 ;
    defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
    defparam PLLInst_0.CLKOS2_CPHASE = 54 ;
    defparam PLLInst_0.CLKOS_FPHASE = 0 ;
    defparam PLLInst_0.CLKOS_CPHASE = 20 ;
    defparam PLLInst_0.CLKOP_FPHASE = 0 ;
    defparam PLLInst_0.CLKOP_CPHASE = 12 ;
    defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
    defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
    defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ;
    defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
    defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ;
    defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ;
    defparam PLLInst_0.CLKOS3_ENABLE = "ENABLED" ;
    defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ;
    defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED" ;
    defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ;
    defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ;
    defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ;
    defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
    defparam PLLInst_0.CLKOS3_DIV = 7 ;
    defparam PLLInst_0.CLKOS2_DIV = 55 ;
    defparam PLLInst_0.CLKOS_DIV = 21 ;
    defparam PLLInst_0.CLKOP_DIV = 13 ;
    defparam PLLInst_0.CLKFB_DIV = 11 ;
    defparam PLLInst_0.CLKI_DIV = 3 ;
    defparam PLLInst_0.FEEDBK_PATH = "CLKOS3" ;
    EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOS3_t), .PHASESEL1(scuba_vlo), 
        .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), 
        .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), 
        .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), 
        .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(CLKOS2_t), 
        .CLKOS3(CLKOS3_t), .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB())
             /* synthesis FREQUENCY_PIN_CLKOS3="89.285714" */
             /* synthesis FREQUENCY_PIN_CLKOS2="11.363636" */
             /* synthesis FREQUENCY_PIN_CLKOS="29.761905" */
             /* synthesis FREQUENCY_PIN_CLKOP="48.076923" */
             /* synthesis FREQUENCY_PIN_CLKI="25.000000" */
             /* synthesis ICP_CURRENT="12" */
             /* synthesis LPF_RESISTOR="16" */;

    assign CLKOS3 = CLKOS3_t;
    assign CLKOS2 = CLKOS2_t;
    assign CLKOS = CLKOS_t;
    assign CLKOP = CLKOP_t;


    // exemplar begin
    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS3 89.285714
    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS2 11.363636
    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 29.761905
    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 48.076923
    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 25.000000
    // exemplar attribute PLLInst_0 ICP_CURRENT 12
    // exemplar attribute PLLInst_0 LPF_RESISTOR 16
    // exemplar end

endmodule
