SCUBA, Version Diamond (64-bit) 3.10.2.115
Thu Mar 14 13:04:33 2019
  
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
  
BEGIN SCUBA Module Synthesis
  
    Issued command   : C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n blk_mem_usb -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type ramdq -device LFE5U-25F -addr_width 11 -data_width 8 -num_words 2048 -cascade 11 -memfile e:/work/lattice/ohm/next186_soc/usb.mem -memformat hex -writemode NORMAL 
    Circuit name     : blk_mem_usb
    Module type      : RAM_DQ
    Module Version   : 7.5
    Ports            : 
    Inputs       : Clock, ClockEn, Reset, WE, Address[10:0], Data[7:0]
    Outputs      : Q[7:0]
    I/O buffer       : not inserted
    Memory file      : e:/work/lattice/ohm/next186_soc/usb.mem
    EDIF output      : blk_mem_usb.edn
    Verilog output   : blk_mem_usb.v
    Verilog template : blk_mem_usb_tmpl.v
    Verilog testbench: tb_blk_mem_usb_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : blk_mem_usb.srp
    Estimated Resource Usage:
            EBR : 1
  
END   SCUBA Module Synthesis

