<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="DAC_SRAM" module="RAM_DP_TRUE" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 08 16 10:44:49.458" version="7.5" type="Module" synthesis="synplify" source_format="Verilog">
  <Package>
		<File name="" type="" modified="2016 08 16 10:44:49.396"/>
		<File name="DAC_SRAM.lpc" type="lpc" modified="2016 08 16 10:44:48.115"/>
		<File name="DAC_SRAM.v" type="top_level_verilog" modified="2016 08 16 10:44:48.146"/>
		<File name="DAC_SRAM_tmpl.v" type="template_verilog" modified="2016 08 16 10:44:48.146"/>
		<File name="tb_DAC_SRAM_tmpl.v" type="testbench_verilog" modified="2016 08 16 10:44:48.161"/>
  </Package>
</DiamondModule>
