<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="fifo" module="fifo" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2017 10 04 18:25:39.731" version="5.8" type="Module" synthesis="synplify" source_format="Verilog HDL">
  <Package>
		<File name="fifo.lpc" type="lpc" modified="2017 10 04 18:25:38.636"/>
		<File name="fifo.v" type="top_level_verilog" modified="2017 10 04 18:25:38.675"/>
		<File name="fifo_tmpl.v" type="template_verilog" modified="2017 10 04 18:25:38.675"/>
		<File name="tb_fifo_tmpl.v" type="testbench_verilog" modified="2017 10 04 18:25:38.690"/>
  </Package>
</DiamondModule>
