/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.9.1.119 */
/* Module Version: 5.8 */
/* Thu Oct 05 10:21:31 2017 */

/* parameterized module instance */
q16 __ (.Data( ), .WrClock( ), .RdClock( ), .WrEn( ), .RdEn( ), 
    .Reset( ), .RPReset( ), .Q( ), .Empty( ), .Full( ));
