[Device]
Family=machxo2
PartType=LCMXO2-7000HE
PartName=LCMXO2-7000HE-4TG144C
SpeedGrade=4
Package=TQFP144
OperatingCondition=COM
Status=S

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
CoreRevision=5.8
ModuleName=dcm
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=10/04/2017
Time=18:09:55

[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=None
Order=None
IO=0
mode=Frequency
CLKI=50
CLKI_DIV=2
BW=2.292
VCO=500.000
fb_mode=CLKOP
CLKFB_DIV=1
FRACN_ENABLE=0
FRACN_DIV=0
DynamicPhase=STATIC
ClkEnable=0
Standby=0
Enable_sel=0
PLLRst=0
PLLMRst=0
ClkOS2Rst=0
ClkOS3Rst=0
LockSig=0
LockStk=0
WBProt=0
OPBypass=0
OPUseDiv=0
CLKOP_DIV=20
FREQ_PIN_CLKOP=25
OP_Tol=0.1
CLKOP_AFREQ=25.000000
CLKOP_PHASEADJ=0
CLKOP_TRIM_POL=Rising
CLKOP_TRIM_DELAY=0
EnCLKOS=1
OSBypass=0
OSUseDiv=0
CLKOS_DIV=5
FREQ_PIN_CLKOS=100
OS_Tol=5.0
CLKOS_AFREQ=100.000000
CLKOS_PHASEADJ=0
CLKOS_TRIM_POL=Rising
CLKOS_TRIM_DELAY=0
EnCLKOS2=1
OS2Bypass=0
OS2UseDiv=0
CLKOS2_DIV=5
FREQ_PIN_CLKOS2=100
OS2_Tol=5.0
CLKOS2_AFREQ=100.000000
CLKOS2_PHASEADJ=225
EnCLKOS3=1
OS3Bypass=0
OS3UseDiv=0
CLKOS3_DIV=10
FREQ_PIN_CLKOS3=50
OS3_Tol=1.0
CLKOS3_AFREQ=50.000000
CLKOS3_PHASEADJ=0

[Command]
cmd_line= -w -n dcm -lang verilog -synth synplify -arch xo2c00 -type pll -fin 50 -fclkop 25 -fclkop_tol 0.1 -fclkos 100 -fclkos_tol 5.0 -fclkos2 100 -fclkos2_tol 5.0 -fclkos3 50 -fclkos3_tol 1.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phases2 225 -phases3 0 -phase_cntl STATIC -fb_mode 1
