-- all messages logged in file hdlparser.log
-- Analyzing Verilog file E:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/cache_controller.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/ddr_186.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/FleaFPGA_2v4_top.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/KB_8042.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/PIC_8259.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/sdram.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/timer8253.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/unit186.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/vga.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/Next186/Next186_ALU.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/Next186/Next186_BIU_2T_delayread.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/Next186/Next186_CPU.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/Next186/Next186_Regs.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/cache.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/DAC_SRAM.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/fifo.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/sr_font.v (VERI-1482)
-- Analyzing Verilog file E:/Work/FleaFPGA/Next186_SoC/dcm.v (VERI-1482)
