/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.9.1.119 */
/* Module Version: 5.8 */
/* C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n fifo -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 512 -width 16 -rwidth 32 -no_enable -pe 31 -pf 290  */
/* Wed Oct 04 18:25:38 2017 */


`timescale 1 ns / 1 ps
module fifo (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q, 
    Empty, Full, AlmostEmpty, AlmostFull)/* synthesis NGD_DRC_MASK=1 */;
    input wire [15:0] Data;
    input wire WrClock;
    input wire RdClock;
    input wire WrEn;
    input wire RdEn;
    input wire Reset;
    input wire RPReset;
    output wire [31:0] Q;
    output wire Empty;
    output wire Full;
    output wire AlmostEmpty;
    output wire AlmostFull;

    wire scuba_vhi;
    wire Empty_int;
    wire Full_int;
    wire scuba_vlo;

    defparam fifo_0_1.FULLPOINTER1 = "0b00111111110000" ;
    defparam fifo_0_1.FULLPOINTER = "0b01000000000000" ;
    defparam fifo_0_1.AFPOINTER1 = "0b00100100000000" ;
    defparam fifo_0_1.AFPOINTER = "0b00100100010000" ;
    defparam fifo_0_1.AEPOINTER1 = "0b00001000000000" ;
    defparam fifo_0_1.AEPOINTER = "0b00000111110000" ;
    defparam fifo_0_1.ASYNC_RESET_RELEASE = "SYNC" ;
    defparam fifo_0_1.GSR = "DISABLED" ;
    defparam fifo_0_1.RESETMODE = "ASYNC" ;
    defparam fifo_0_1.REGMODE = "NOREG" ;
    defparam fifo_0_1.CSDECODE_R = "0b11" ;
    defparam fifo_0_1.CSDECODE_W = "0b11" ;
    defparam fifo_0_1.DATA_WIDTH_R = 18 ;
    defparam fifo_0_1.DATA_WIDTH_W = 9 ;
    FIFO8KB fifo_0_1 (.DI0(Data[0]), .DI1(Data[1]), .DI2(Data[2]), .DI3(Data[3]), 
        .DI4(Data[4]), .DI5(Data[5]), .DI6(Data[6]), .DI7(Data[7]), .DI8(Data[8]), 
        .DI9(scuba_vlo), .DI10(scuba_vlo), .DI11(scuba_vlo), .DI12(scuba_vlo), 
        .DI13(scuba_vlo), .DI14(scuba_vlo), .DI15(scuba_vlo), .DI16(scuba_vlo), 
        .DI17(scuba_vlo), .CSW0(scuba_vhi), .CSW1(scuba_vhi), .CSR0(scuba_vhi), 
        .CSR1(scuba_vhi), .FULLI(Full_int), .EMPTYI(Empty_int), .WE(WrEn), 
        .RE(RdEn), .ORE(RdEn), .CLKW(WrClock), .CLKR(RdClock), .RST(Reset), 
        .RPRST(RPReset), .DO0(Q[16]), .DO1(Q[17]), .DO2(Q[18]), .DO3(Q[19]), 
        .DO4(Q[20]), .DO5(Q[21]), .DO6(Q[22]), .DO7(Q[23]), .DO8(Q[24]), 
        .DO9(Q[0]), .DO10(Q[1]), .DO11(Q[2]), .DO12(Q[3]), .DO13(Q[4]), 
        .DO14(Q[5]), .DO15(Q[6]), .DO16(Q[7]), .DO17(Q[8]), .EF(Empty_int), 
        .AEF(AlmostEmpty), .AFF(AlmostFull), .FF(Full_int));

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    defparam fifo_1_0.FULLPOINTER1 = "0b00000000000000" ;
    defparam fifo_1_0.FULLPOINTER = "0b11111111110000" ;
    defparam fifo_1_0.AFPOINTER1 = "0b00000000000000" ;
    defparam fifo_1_0.AFPOINTER = "0b11111111110000" ;
    defparam fifo_1_0.AEPOINTER1 = "0b00000000000000" ;
    defparam fifo_1_0.AEPOINTER = "0b11111111110000" ;
    defparam fifo_1_0.ASYNC_RESET_RELEASE = "SYNC" ;
    defparam fifo_1_0.GSR = "DISABLED" ;
    defparam fifo_1_0.RESETMODE = "ASYNC" ;
    defparam fifo_1_0.REGMODE = "NOREG" ;
    defparam fifo_1_0.CSDECODE_R = "0b11" ;
    defparam fifo_1_0.CSDECODE_W = "0b11" ;
    defparam fifo_1_0.DATA_WIDTH_R = 18 ;
    defparam fifo_1_0.DATA_WIDTH_W = 9 ;
    FIFO8KB fifo_1_0 (.DI0(Data[9]), .DI1(Data[10]), .DI2(Data[11]), .DI3(Data[12]), 
        .DI4(Data[13]), .DI5(Data[14]), .DI6(Data[15]), .DI7(scuba_vlo), 
        .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo), .DI11(scuba_vlo), 
        .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), .DI15(scuba_vlo), 
        .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), .CSW1(scuba_vhi), 
        .CSR0(scuba_vhi), .CSR1(scuba_vhi), .FULLI(Full_int), .EMPTYI(Empty_int), 
        .WE(WrEn), .RE(RdEn), .ORE(RdEn), .CLKW(WrClock), .CLKR(RdClock), 
        .RST(Reset), .RPRST(RPReset), .DO0(Q[25]), .DO1(Q[26]), .DO2(Q[27]), 
        .DO3(Q[28]), .DO4(Q[29]), .DO5(Q[30]), .DO6(Q[31]), .DO7(), .DO8(), 
        .DO9(Q[9]), .DO10(Q[10]), .DO11(Q[11]), .DO12(Q[12]), .DO13(Q[13]), 
        .DO14(Q[14]), .DO15(Q[15]), .DO16(), .DO17(), .EF(), .AEF(), .AFF(), 
        .FF());

    assign Empty = Empty_int;
    assign Full = Full_int;


    // exemplar begin
    // exemplar end

endmodule
