<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="cache" module="cache" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 09 26 15:50:43.749" version="7.5" type="Module" synthesis="synplify" source_format="Verilog HDL">
  <Package>
		<File name="" type="" modified="2016 09 26 15:50:43.670"/>
		<File name="cache.lpc" type="lpc" modified="2016 09 26 15:50:42.733"/>
		<File name="cache.v" type="top_level_verilog" modified="2016 09 26 15:50:42.780"/>
		<File name="cache_bootload.mem" type="mem" modified="2016 09 26 15:50:31.695"/>
		<File name="cache_tmpl.v" type="template_verilog" modified="2016 09 26 15:50:42.780"/>
		<File name="tb_cache_tmpl.v" type="testbench_verilog" modified="2016 09 26 15:50:42.780"/>
  </Package>
</DiamondModule>
