SCUBA, Version Diamond (64-bit) 3.5.1.302
Mon Sep 26 15:50:42 2016

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2015 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\3.5_x64\ispfpga\bin\nt64\scuba.exe -w -n cache -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-7000HE -aaddr_width 11 -widtha 32 -baddr_width 11 -widthb 32 -anum_words 2048 -bnum_words 2048 -byte 8 -cascade -1 -memfile cache_bootload.mem -memformat hex -writemodeA READBEFOREWRITE -writemodeB READBEFOREWRITE 
    Circuit name     : cache
    Module type      : RAM_DP_TRUE
    Module Version   : 7.5
    Ports            : 
	Inputs       : DataInA[31:0], DataInB[31:0], ByteEnA[3:0], ByteEnB[3:0], AddressA[10:0], AddressB[10:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
	Outputs      : QA[31:0], QB[31:0]
    I/O buffer       : not inserted
    Memory file      : cache_bootload.mem
    EDIF output      : cache.edn
    Verilog output   : cache.v
    Verilog template : cache_tmpl.v
    Verilog testbench: tb_cache_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : cache.srp
    Element Usage    :
        FD1P3DX : 2
          MUX21 : 64
          DP8KC : 8
    Estimated Resource Usage:
            LUT : 64
            EBR : 8
            Reg : 2
