<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="q16" module="q16" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2017 10 05 10:21:32.439" version="5.8" type="Module" synthesis="synplify" source_format="Verilog HDL">
  <Package>
		<File name="q16.lpc" type="lpc" modified="2017 10 05 10:21:31.751"/>
		<File name="q16.v" type="top_level_verilog" modified="2017 10 05 10:21:31.783"/>
		<File name="q16_tmpl.v" type="template_verilog" modified="2017 10 05 10:21:31.783"/>
		<File name="tb_q16_tmpl.v" type="testbench_verilog" modified="2017 10 05 10:21:31.798"/>
  </Package>
</DiamondModule>
