/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.5.1.302 */
/* Module Version: 5.8 */
/* Mon Sep 26 11:25:04 2016 */

/* parameterized module instance */
sndfifo __ (.Data( ), .WrClock( ), .RdClock( ), .WrEn( ), .RdEn( ), 
    .Reset( ), .RPReset( ), .Q( ), .Empty( ), .Full( ), .AlmostEmpty( ), 
    .AlmostFull( ));
