Starting process: Module

Starting process: 

SCUBA, Version Diamond (64-bit) 3.5.1.302
Mon Sep 26 11:40:13 2016

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2015 Lattice Semiconductor Corporation,  All rights reserved.

BEGIN SCUBA Module Synthesis

    Issued command   : C:\lscc\diamond\3.5_x64\ispfpga\bin\nt64\scuba.exe -w -n dcm1 -lang verilog -synth synplify -arch xo2c00 -type pll -fin 50 -fclkop 29.4912 -fclkop_tol 2.0 -fclkos 11.289600 -fclkos_tol 1.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phase_cntl STATIC -fb_mode 1 
    Circuit name     : dcm1
    Module type      : pll
    Module Version   : 5.7
    Ports            : 
	Inputs       : CLKI
	Outputs      : CLKOP, CLKOS
    I/O buffer       : not inserted
    EDIF output      : dcm1.edn
    Verilog output   : dcm1.v
    Verilog template : dcm1_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : dcm1.srp
    Estimated Resource Usage:

END   SCUBA Module Synthesis

File: dcm1.lpc created.


End process: completed successfully.


Total Warnings:  0

Total Errors:  0


