SCUBA, Version Diamond (64-bit) 3.9.1.119
Thu Oct 05 10:21:31 2017
  
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
  
BEGIN SCUBA Module Synthesis
  
    Issued command   : C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n q16 -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 8 -width 8 -rwidth 8 -pfu_fifo -no_enable -pe -1 -pf -1 
    Circuit name     : q16
    Module type      : ebfifo
    Module Version   : 5.8
    Ports            : 
    Inputs       : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
    Outputs      : Q[7:0], Empty, Full
    I/O buffer       : not inserted
    EDIF output      : q16.edn
    Verilog output   : q16.v
    Verilog template : q16_tmpl.v
    Verilog testbench: tb_q16_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : q16.srp
    Estimated Resource Usage:
            LUT : 48
           DRAM : 2
            Reg : 50
  
END   SCUBA Module Synthesis

