<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="sndfifo" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 09 26 11:25:06.118" version="5.8" type="Module" synthesis="synplify" source_format="Verilog">
  <Package>
		<File name="sndfifo.lpc" type="lpc" modified="2016 09 26 11:25:04.446"/>
		<File name="sndfifo.v" type="top_level_verilog" modified="2016 09 26 11:25:04.493"/>
		<File name="sndfifo_tmpl.v" type="template_verilog" modified="2016 09 26 11:25:04.493"/>
		<File name="tb_sndfifo_tmpl.v" type="testbench_verilog" modified="2016 09 26 11:25:04.493"/>
  </Package>
</DiamondModule>
