[Device]
Family=machxo2
PartType=LCMXO2-7000HE
PartName=LCMXO2-7000HE-4TG144C
SpeedGrade=4
Package=TQFP144
OperatingCondition=COM
Status=S

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=RAM_DP_TRUE
CoreRevision=7.5
ModuleName=cache
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=09/26/2016
Time=15:50:42

[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
RAddress=2048
RData=32
WAddress=2048
WData=32
ROutputEn=0
RClockEn=0
WOutputEn=0
WClockEn=0
enByte=1
ByteSize=8
Optimization=Speed
Reset=Sync
Reset1=Sync
Init=mem
MemFile=cache_bootload.mem
MemFormat=hex
EnECC=0
Pipeline=1
WriteA=ReadBeforeWrite
WriteB=ReadBeforeWrite
init_data=0

[FilesGenerated]
cache_bootload.mem=mem

[Command]
cmd_line= -w -n cache -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-7000HE -aaddr_width 11 -widtha 32 -baddr_width 11 -widthb 32 -anum_words 2048 -bnum_words 2048 -byte 8 -cascade -1 -memfile cache_bootload.mem -memformat hex -writemodeA READBEFOREWRITE -writemodeB READBEFOREWRITE
