
module FleaFPGA_2v4(
//    -- System clock and reset
	input sys_clock, // main clock input from external clock source
	input sys_reset, // main clock input from external RC reset circuit

//    -- On-board user buttons and status LEDs
	input n_pb1,  
	input n_pb2,
	output n_led1,
	output n_led2,
	output n_led3,
	output n_led4,

//    -- USB Host (CH376T) interface
	output host_reset,
	output host_spi,
	input host_nInt,
	output host_sdi,
	input host_sdo,
	output host_sck,
	output host_cs,
	output host_tx_o,
	input host_rx_i,
	
//    -- USB Slave (FT230x) interface 
	output slave_tx_o,
	input slave_rx_i,
	
//    -- User GPIO (18 I/O pins) Header
	inout [18:1]GPIO,  // GPIO Header pins available as one data block
	
//	-- SDRAM interface (For use with 16Mx16bit or 32Mx16bit SDR DRAM, depending on version)
	output Dram_Clk,	// clock to SDRAM
	output Dram_n_Ras,  // SDRAM RAS
	output Dram_n_Cas,	// SDRAM CAS
	output Dram_n_We,	// SDRAM write-enable
	output [1:0]Dram_BA,	// SDRAM bank-address
	output [12:0]Dram_Addr,	// SDRAM address bus
	inout [15:0]Dram_Data,	// data bus to/from SDRAM
	output Dram_n_cs, 
	output Dram_DQMH,
	output Dram_DQML,
	
//	-- VGA interface (Note: 12-bit color organized as RGB = 4/4/4-bits)
	output vga_vs,
	output vga_hs,
	output [3:0]vga_red,
	output [3:0]vga_green,
	output [3:0]vga_blue,
	
//	-- SD/MMC Interface (Support either SPI or nibble-mode)
	input mmc_dat1,
	input mmc_dat2,
	output mmc_n_cs,
	output mmc_clk,
	output mmc_mosi,
	input mmc_miso,

//	-- Audio out (stereo-PWM) interface	
	output Audio_l,
	output Audio_r,
	
//	-- PS2 interface (Both ports accessible via Y-splitter cable)
	inout PS2_clk1,
	inout PS2_data1,
	inout PS2_clk2,
	inout PS2_data2
    );
	
//  -- Housekeeping logic for unwanted peripherals on FleaFPGA board goes here!!!
//  -- (Note: comment out any of the following code lines if peripheral is required)
	wire [3:0]LED;
	assign host_cs = 1'b1; 	// -- USB host SPI interface disabled
	assign {n_led4, n_led3, n_led2, n_led1} = ~LED;

	system sys_inst
	(
		.CLK_50MHZ(sys_clock),
		.VGA_R(vga_red),
		.VGA_G(vga_green),
		.VGA_B(vga_blue),
		.VGA_HSYNC(vga_hs),
		.VGA_VSYNC(vga_vs),
		.sdr_CLK_out(Dram_Clk),
		.sdr_n_CS_WE_RAS_CAS({Dram_n_cs, Dram_n_We, Dram_n_Ras, Dram_n_Cas}),
		.sdr_BA(Dram_BA),
		.sdr_ADDR(Dram_Addr),
		.sdr_DATA(Dram_Data),
		.sdr_DQM({Dram_DQMH, Dram_DQML}),
		.LED(LED),
		.BTN_RESET(!n_pb1),
		.BTN_NMI(!n_pb2),
		.RS232_DCE_RXD(slave_rx_i),
		.RS232_DCE_TXD(slave_tx_o),
		.SD_n_CS(mmc_n_cs),
		.SD_DI(mmc_mosi),
		.SD_CK(mmc_clk),
		.SD_DO(mmc_miso),
		.AUD_L(Audio_l),
		.AUD_R(Audio_r),
	 	.PS2_CLK1(PS2_clk1),
		.PS2_CLK2(PS2_clk2),
		.PS2_DATA1(PS2_data1),
		.PS2_DATA2(PS2_data2),
		.RS232_HOST_RXD(host_rx_i),
		.RS232_HOST_TXD(host_tx_o),
		.RS232_HOST_RST(host_reset),
		.RS232_EXT_RXD(GPIO[1]),
		.RS232_EXT_TXD(GPIO[2]),
		.GPIO(GPIO[17:10])
	);
 
endmodule
