[Device]
Family=machxo2
PartType=LCMXO2-7000HE
PartName=LCMXO2-7000HE-4TG144C
SpeedGrade=4
Package=TQFP144
OperatingCondition=COM
Status=S

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=RAM_DP_TRUE
CoreRevision=7.5
ModuleName=DAC_SRAM
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=08/16/2016
Time=10:44:48

[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
RAddress=1024
RData=8
WAddress=256
WData=32
ROutputEn=0
RClockEn=0
WOutputEn=0
WClockEn=0
enByte=0
ByteSize=9
Optimization=Speed
Reset=Sync
Reset1=Sync
Init=0
MemFile=
MemFormat=hex
EnECC=0
Pipeline=0
WriteA=Normal
WriteB=Normal
init_data=0

[FilesGenerated]
=mem

[Command]
cmd_line= -w -n DAC_SRAM -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-7000HE -aaddr_width 10 -widtha 8 -baddr_width 8 -widthb 32 -anum_words 1024 -bnum_words 256 -cascade -1 -mem_init0 -writemodeA NORMAL -writemodeB NORMAL
