Starting process: module

Starting process: 

SCUBA, Version Diamond (64-bit) 3.9.1.119
Wed Oct 04 18:25:38 2017

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.

BEGIN SCUBA Module Synthesis

    Issued command   : C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n fifo -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 512 -width 16 -rwidth 32 -no_enable -pe 31 -pf 290 
    Circuit name     : fifo
    Module type      : ebfifo
    Module Version   : 5.8
    Ports            : 
	Inputs       : Data[15:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
	Outputs      : Q[31:0], Empty, Full, AlmostEmpty, AlmostFull
    I/O buffer       : not inserted
    EDIF output      : fifo.edn
    Verilog output   : fifo.v
    Verilog template : fifo_tmpl.v
    Verilog testbench: tb_fifo_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : fifo.srp
    Estimated Resource Usage:
            EBR : 2

END   SCUBA Module Synthesis

File: fifo.lpc created.


End process: completed successfully.


Total Warnings:  0

Total Errors:  0


