SCUBA, Version Diamond (64-bit) 3.5.1.302
Tue Aug 16 10:43:59 2016

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2015 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\3.5_x64\ispfpga\bin\nt64\scuba.exe -w -n sr_font -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-7000HE -aaddr_width 12 -widtha 8 -baddr_width 12 -widthb 8 -anum_words 4096 -bnum_words 4096 -cascade -1 -memfile e:/work/fleafpga/next186_soc/font.mem -memformat hex -writemodeA NORMAL -writemodeB NORMAL 
    Circuit name     : sr_font
    Module type      : RAM_DP_TRUE
    Module Version   : 7.5
    Ports            : 
	Inputs       : DataInA[7:0], DataInB[7:0], AddressA[11:0], AddressB[11:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
	Outputs      : QA[7:0], QB[7:0]
    I/O buffer       : not inserted
    Memory file      : e:/work/fleafpga/next186_soc/font.mem
    EDIF output      : sr_font.edn
    Verilog output   : sr_font.v
    Verilog template : sr_font_tmpl.v
    Verilog testbench: tb_sr_font_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : sr_font.srp
    Element Usage    :
          DP8KC : 4
    Estimated Resource Usage:
            EBR : 4
