`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:25:31 11/20/2014 
// Design Name: 
// Module Name:    PapilioProMain 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module Nexys4_Next186Soc
	(
		input CLK100MHZ,
		output [3:0]vgaRed,
		output [3:0]vgaGreen,
		output [3:0]vgaBlue,
		output Hsync,
		output Vsync,
		output [15:0]LED,
		output [22:0]MemAdr,
		inout [15:0]MemDB,
		output RamCLK,
		output RamADVn,
		output RamCEn,
		output RamCRE,
		output RamOEn,
		output RamWEn,
		output RamLBn,
		output RamUBn,
		input RamWait,
		input btnD,
		input btnL,
		input RsRx,
		output RsTx,
		output ampPWM,
		output ampSD,
//		output AUDIO_R,
		inout PS2Clk,
		inout PS2Data,
		output JC0,
		output JC1,
		inout JC2,
		inout JC3,
      input JC4,
      output JC5,
		output sdReset,
		output sdData3,
		output sdCmd,
		output sdSCK,
		input sdData0,

      inout [7:0]JA
	);

	wire CLK_PSR;
	wire CLK_PSR_ON;
	wire [1:0]rlo;
	wire [1:0]glo;
	wire [1:0]blo;
	assign LED[15:8] = 8'h00;
	assign sdReset = 1'b0;
	assign ampSD = 1'b1;
	assign ampPWM = JC0; 

   ODDR #(
      .DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
      .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
      .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
   ) ODDR_inst (
      .Q(RamCLK),    // 1-bit DDR output
      .C(CLK_PSR),   // 1-bit clock input
      .CE(1'b1), 	 	// 1-bit clock enable input
      .D1(CLK_PSR_ON), 	// 1-bit data input (positive edge)
      .D2(1'b0), 		// 1-bit data input (negative edge)
      .R(1'b0),   	// 1-bit reset
      .S(1'b0)    	// 1-bit set
   );


	system sys_inst
	(
		.CLK_IN(CLK100MHZ),
		.VGA_R({vgaRed, rlo}),
		.VGA_G({vgaGreen, glo}),
		.VGA_B({vgaBlue, blo}),
		.VGA_HSYNC(Hsync),
		.VGA_VSYNC(Vsync),
		.mem_CLK_out(CLK_PSR),
		.mem_CLK_on(CLK_PSR_ON),
		.MemAdr(MemAdr),
		.MemDB(MemDB),
		.RamADVn(RamADVn),
		.RamCEn(RamCEn),
		.RamCRE(RamCRE),
		.RamOEn(RamOEn),
		.RamWEn(RamWEn),
		.RamLBn(RamLBn),
		.RamUBn(RamUBn),
		.RamWait(RamWait),
		.LED(LED[7:0]),

		.BTN_RESET(btnD),
		.BTN_NMI(btnL),
		.RS232_DCE_RXD(RsRx),
		.RS232_DCE_TXD(RsTx),
		.SD_n_CS(sdData3),
		.SD_DI(sdCmd),
		.SD_CK(sdSCK),
		.SD_DO(sdData0),
		.AUD_L(JC0),
		.AUD_R(JC1),
	 	.PS2_CLK1(JC3),
		.PS2_DATA1(JC2),
		.PS2_DATA2(PS2Data),
		.PS2_CLK2(PS2Clk),
      
		.RS232_EXT_RXD(JC4),
		.RS232_EXT_TXD(JC5),
		.RS232_HOST_RXD(),
		.RS232_HOST_TXD(),
		.RS232_HOST_RST(),

      .GPIO(JA)
	);

endmodule
