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#!/bin/sh
cp ../../../sr_font.mif .

rm -rf simv* csrc DVEfiles AN.DB

echo "Compiling Core Verilog UNISIM/Behavioral model"
vlogan +v2k  ../../implement/results/routed.v

echo "Compiling Test Bench Files"
vhdlan    ../bmg_tb_pkg.vhd
vhdlan    ../random.vhd
vhdlan    ../data_gen.vhd
vhdlan    ../addr_gen.vhd
vhdlan    ../checker.vhd
vhdlan    ../bmg_stim_gen.vhd
vhdlan    ../sr_font_synth.vhd 
vhdlan    ../sr_font_tb.vhd


echo "Elaborating Design"
vcs +neg_tchk +vcs+lic+wait -debug sr_font_tb glbl

echo "Simulating Design"
./simv -ucli -i ucli_commands.key
dve -session vcs_session.tcl
