`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:25:31 11/20/2014 
// Design Name: 
// Module Name:    PapilioProMain 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module Pipistrello_Next186Soc
	(
		input CLK_IN,
		output [3:0]TMDS,
		output [3:0]TMDSB,
		
		output LED0,
		output LED1,
		output LED2,
		output LED3,
		output LED4,
		input switch,
		input usb_rxd,
		output usb_txd,
		output audio_l,
		output audio_r,
		inout Wing_A0,	// clk1
		inout Wing_A1,	// dat1
		inout Wing_A2,	// dat2
		inout Wing_A3,	// clk2
		input Wing_A6, // RS232_EXT_RXD,
		output Wing_A7, // RS232_EXT_TXD,
      inout Wing_A8,
      inout Wing_A9,
      inout Wing_A10,
      inout Wing_A11,
      inout Wing_A12,
      inout Wing_A13,
      inout Wing_A14,
      inout Wing_A15,
		
		output sd_cs,
		output sd_mosi,
		output sd_sck,
		input sd_miso,

		output [12:0]mcb3_dram_a,
		output [1:0]mcb3_dram_ba,
		output mcb3_dram_cas_n,
		output mcb3_dram_ras_n,
		output mcb3_dram_we_n,
		output mcb3_dram_ck_n,
		output mcb3_dram_ck,
		output mcb3_dram_cke,
		output mcb3_dram_dm,
		output mcb3_dram_udm,
		inout [15:0]mcb3_dram_dq,
		inout mcb3_dram_dqs,
		inout mcb3_dram_udqs,
		inout mcb3_rzq		
	);

 	 wire [5:0]VGA_R;
	 wire [5:0]VGA_G;
	 wire [5:0]VGA_B;
	 wire VGA_HSYNC;
	 wire VGA_VSYNC;
	 wire clk_25;
	 wire clk_50;
	 wire clk_250;
	 wire de;
	 wire pll_locked;
	 wire l7, l5, l4;

	system sys_inst
	(
		.CLK_50MHZ(CLK_IN),
		.VGA_R(VGA_R),
		.VGA_G(VGA_G),
		.VGA_B(VGA_B),
		.VGA_HSYNC(VGA_HSYNC),
		.VGA_VSYNC(VGA_VSYNC),
		.clk_25(clk_25),
		.clk_50(clk_50),
		.clk_250(clk_250),
		.de(de),
		.pll_locked(pll_locked),
		
		.LED({l7, LED4, l5, l4, LED3, LED2, LED1, LED0}),
		.BTN_RESET(switch),
		.BTN_NMI(1'b0),
		.RS232_DCE_RXD(usb_rxd),
		.RS232_DCE_TXD(usb_txd),
      .RS232_EXT_RXD(Wing_A6),
      .RS232_EXT_TXD(Wing_A7),
		.SD_n_CS(sd_cs),
		.SD_DI(sd_mosi),
		.SD_CK(sd_sck),
		.SD_DO(sd_miso),
		.AUD_L(audio_l),
		.AUD_R(audio_r),
	 	.PS2_CLK1(Wing_A0),
		.PS2_DATA1(Wing_A1),
		.PS2_CLK2(Wing_A3),
		.PS2_DATA2(Wing_A2),
		.RS232_HOST_RXD(1'b0),
      .GPIO({Wing_A15, Wing_A14, Wing_A13, Wing_A12, Wing_A11, Wing_A10, Wing_A9, Wing_A8}),
		
		.mcb3_dram_a(mcb3_dram_a),
		.mcb3_dram_ba(mcb3_dram_ba),
		.mcb3_dram_cas_n(mcb3_dram_cas_n),
		.mcb3_dram_ras_n(mcb3_dram_ras_n),
		.mcb3_dram_we_n(mcb3_dram_we_n),
		.mcb3_dram_ck_n(mcb3_dram_ck_n),
		.mcb3_dram_ck(mcb3_dram_ck),
		.mcb3_dram_cke(mcb3_dram_cke),
		.mcb3_dram_dm(mcb3_dram_dm),
		.mcb3_dram_udm(mcb3_dram_udm),
		.mcb3_dram_dq(mcb3_dram_dq),
		.mcb3_dram_dqs(mcb3_dram_dqs),
		.mcb3_dram_udqs(mcb3_dram_udqs),
		.mcb3_rzq(mcb3_rzq)
		
//		.RS232_HOST_TXD(host_tx_o),
//		.RS232_HOST_RST(host_reset)
	);
	
	HDMI_OUT HDMI_OUT_inst
	(
		.clk(clk_25),		// bufg, from PLL_BASE
		.clk2x(clk_50),	// bufg, from PLL_BASE
		.clk10x(clk_250),	// unbuffered, from PLL_BASE
		.pll_locked(pll_locked), // from PLL_BASE
		.R({VGA_R, 2'b00}),
		.G({VGA_G, 2'b00}),
		.B({VGA_B, 2'b00}),
		.hsync(VGA_HSYNC),
		.vsync(VGA_VSYNC),
		.de(de),
		.TMDS(TMDS),
		.TMDSB(TMDSB)
	);

endmodule
