

--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
-- 
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
-- 
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- including negligence, or under any other theory of
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--
--------------------------------------------------------------------------------
--
--
-- Description:
--   This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library unisim;
use unisim.vcomponents.all;

--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity dpstack_exdes is
  PORT (
      A          : IN  STD_LOGIC_VECTOR(5-1-(4*0*boolean'pos(5>4)) downto 0)
                 := (OTHERS => '0');
      D          : IN  STD_LOGIC_VECTOR(32-1 downto 0)                := (OTHERS => '0');
      DPRA       : IN  STD_LOGIC_VECTOR(5-1 downto 0)           := (OTHERS => '0');
      SPRA       : IN  STD_LOGIC_VECTOR(5-1 downto 0)           := (OTHERS => '0');
      CLK        : IN  STD_LOGIC                                                := '0';
      WE         : IN  STD_LOGIC                                                := '0';
      I_CE       : IN  STD_LOGIC                                                := '1';
      QSPO_CE    : IN  STD_LOGIC                                                := '1';
      QDPO_CE    : IN  STD_LOGIC                                                := '1';
      QDPO_CLK   : IN  STD_LOGIC                                                := '0';
      QSPO_RST   : IN  STD_LOGIC                                                := '0';
      QDPO_RST   : IN  STD_LOGIC                                                := '0';
      QSPO_SRST  : IN  STD_LOGIC                                                := '0';
      QDPO_SRST  : IN  STD_LOGIC                                                := '0';
      SPO        : OUT STD_LOGIC_VECTOR(32-1 downto 0);
      DPO        : OUT STD_LOGIC_VECTOR(32-1 downto 0);
      QSPO       : OUT STD_LOGIC_VECTOR(32-1 downto 0);
      QDPO       : OUT STD_LOGIC_VECTOR(32-1 downto 0)
      );

end dpstack_exdes;



architecture xilinx of dpstack_exdes is

    SIGNAL CLK_i    : std_logic;
    
  component dpstack is
  PORT (

      DPRA                    : IN  STD_LOGIC_VECTOR(5-1 downto 0)           := (OTHERS => '0');
      CLK                     : IN STD_LOGIC;
      WE                      : IN  STD_LOGIC;
      DPO                     : OUT STD_LOGIC_VECTOR(32-1 downto 0);
      A                       : IN  STD_LOGIC_VECTOR(5-1-(4*0*boolean'pos(5>4)) downto 0)
                              := (OTHERS => '0');
      D                       : IN  STD_LOGIC_VECTOR(32-1 downto 0)                := (OTHERS => '0')

);
  end component;


begin

  dmg0 : dpstack
    port map (

      DPRA                    => DPRA,
      CLK                     => CLK_i,
      WE                      => WE,
      DPO                     => DPO,
      A                       => A,
      D                       => D

      );

clk_buf: bufg
    PORT map(
      i => CLK,
      o => CLK_i
      );



end xilinx;
