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[/] [open8_urisc/] [trunk/] [VHDL/] [vector_tx.vhd] - Rev 285
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-- Copyright (c)2020 Jeremy Seth Henry -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- * Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution, -- where applicable (as part of a user interface, debugging port, etc.) -- -- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY -- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- VHDL Entity: vector_tx -- Description: Reads the pushbuttons and switches on the DE1-SOC board and -- sends a vector command and argument to a vector_rx receiver -- which executes them in lieu of a parallel controller. -- -- Revision History -- Author Date Change ------------------ -------- --------------------------------------------------- -- Seth Henry 05/06/20 Added version block -- Seth Henry 04/07/21 Modified to replace hard-coded blocks with true -- argument inputs. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.std_logic_misc.all; library work; use work.open8_pkg.all; entity vector_tx is generic( Button_Level : std_logic; Bit_Rate : real; Enable_Parity : boolean; Parity_Odd_Even_n : std_logic; Sys_Freq : real; Reset_Level : std_logic ); port( Clock : in std_logic; Reset : in std_logic; -- Tx_Enable : in std_logic; Tx_Command : in DATA_TYPE; Tx_Arg_Lower : in DATA_TYPE; Tx_Arg_Upper : in DATA_TYPE; -- Tx_Busy : out std_logic; -- Tx_Out : out std_logic; Tx_FC : in std_logic := '1' ); end entity; architecture behave of vector_tx is signal Command_Buffer : DATA_TYPE := x"00"; signal Arg_Lower_Buffer : DATA_TYPE := x"00"; signal Arg_Upper_Buffer : DATA_TYPE := x"00"; type VECTOR_TX_STATES is (IDLE, SEND_CMD, WAIT_CMD, SEND_ARG_LB, WAIT_ARG_LB, SEND_ARG_UB, WAIT_ARG_UB, SEND_SUM, WAIT_SUM ); signal Vector_State : VECTOR_TX_STATES := IDLE; constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate); constant MAGIC_NUM : DATA_TYPE := x"4D"; signal Checksum : DATA_TYPE := x"00"; signal Tx_Data : DATA_TYPE := x"00"; signal Tx_Valid : std_logic := '0'; signal Tx_Done : std_logic := '0'; begin TX_FSM_proc: process( Clock, Reset ) begin if( Reset = Reset_Level )then Vector_State <= IDLE; Command_Buffer <= x"00"; Arg_Lower_Buffer <= x"00"; Arg_Upper_Buffer <= x"00"; Tx_Busy <= '0'; Tx_Data <= x"00"; Tx_Valid <= '0'; elsif( rising_edge(Clock) )then Tx_Busy <= '1'; Tx_Data <= x"00"; Tx_Valid <= '0'; case( Vector_State )is when IDLE => Tx_Busy <= '0'; Checksum <= MAGIC_NUM; if( Tx_Enable = '1' )then Command_Buffer <= Tx_Command; Arg_Lower_Buffer <= Tx_Arg_Lower; Arg_Upper_Buffer <= Tx_Arg_Upper; Vector_State <= SEND_CMD; end if; when SEND_CMD => Tx_Data <= Command_Buffer; Tx_Valid <= '1'; Checksum <= Checksum + Command_Buffer; Vector_State <= WAIT_CMD; when WAIT_CMD => if( Tx_Done = '1' )then Vector_State <= SEND_ARG_LB; end if; when SEND_ARG_LB => Tx_Data <= Arg_Lower_Buffer; Tx_Valid <= '1'; Checksum <= Checksum + Arg_Lower_Buffer; Vector_State <= WAIT_ARG_LB; when WAIT_ARG_LB => if( Tx_Done = '1' )then Vector_State <= SEND_ARG_UB; end if; when SEND_ARG_UB => Tx_Data <= Arg_Upper_Buffer; Tx_Valid <= '1'; Checksum <= Checksum + Arg_Upper_Buffer; Vector_State <= WAIT_ARG_UB; when WAIT_ARG_UB => if( Tx_Done = '1' )then Vector_State <= SEND_SUM; end if; when SEND_SUM => Tx_Data <= Checksum; Tx_Valid <= '1'; Vector_State <= WAIT_SUM; when WAIT_SUM => if( Tx_Done = '1' )then Vector_State <= IDLE; end if; end case; end if; end process; U_TX : entity work.async_ser_tx generic map( Reset_Level => Reset_Level, Enable_Parity => Enable_Parity, Parity_Odd_Even_n => Parity_Odd_Even_n, Clock_Divider => BAUD_RATE_DIV ) port map( Clock => Clock, Reset => Reset, -- Tx_Data => Tx_Data, Tx_Valid => Tx_Valid, -- Tx_Out => Tx_Out, Tx_Done => Tx_Done ); end architecture;
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